arm_coresight: define ARM_CS_CIDR_CLASS()

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 1c96dc87ac8c0952d224c5702ef07473a98e0ef6..5c598f16e34a47ae41a1be6a22a74eb86968ab13 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -65,6 +65,10 @@
 
 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
 
+/* Fields of DP_DPIDR register */
+#define DP_DPIDR_VERSION_SHIFT 12
+#define DP_DPIDR_VERSION_MASK  (0xFUL << DP_DPIDR_VERSION_SHIFT)
+
 /* Fields of the DP's AP ABORT register */
 #define DAPABORT        (1UL << 0)
 #define STKCMPCLR       (1UL << 1) /* SWD-only */
@@ -89,6 +93,8 @@
 #define CSYSPWRUPREQ    (1UL << 30)
 #define CSYSPWRUPACK    (1UL << 31)
 
+#define DP_DLPIDR_PROTVSN      1u
+
 #define DP_SELECT_APSEL 0xFF000000
 #define DP_SELECT_APBANK 0x000000F0
 #define DP_SELECT_DPBANK 0x0000000F
@@ -336,6 +342,11 @@ struct adiv5_dap {
        bool multidrop_dp_id_valid;
        /** TINSTANCE field of multidrop_targetsel has been configured */
        bool multidrop_instance_id_valid;
+
+       /**
+        * Record if enter in SWD required passing through DORMANT
+        */
+       bool switch_through_dormant;
 };
 
 /**