cortex: Set default memaccess_tck only during examine

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index e6aabdd2838af709d69f055e5414eeac9e3cc977..d5fba3bbc51a7302beeb1e21d0b4661ff39a9e93 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -122,11 +122,30 @@
 #define CSW_SPROT           (1UL << 30)
 #define CSW_DBGSWENABLE     (1UL << 31)
 
+/* Fields of the MEM-AP's IDR register */
+#define IDR_REV     (0xFUL << 28)
+#define IDR_JEP106  (0x7FFUL << 17)
+#define IDR_CLASS   (0xFUL << 13)
+#define IDR_VARIANT (0xFUL << 4)
+#define IDR_TYPE    (0xFUL << 0)
+
+#define IDR_JEP106_ARM 0x04760000
+
 /**
  * This represents an ARM Debug Interface (v5) Access Port (AP).
  * Most common is a MEM-AP, for memory access.
  */
 struct adiv5_ap {
+       /**
+        * DAP this AP belongs to.
+        */
+       struct adiv5_dap *dap;
+
+       /**
+        * Number of this AP.
+        */
+       uint8_t ap_num;
+
        /**
         * Default value for (MEM-AP) AP_REG_CSW register.
         */
@@ -182,7 +201,7 @@ struct adiv5_ap {
 struct adiv5_dap {
        const struct dap_ops *ops;
 
-       struct arm_jtag *jtag_info;
+       struct jtag_tap *tap;
        /* Control config */
        uint32_t dp_ctrl_stat;
 
@@ -244,11 +263,6 @@ struct adiv5_dap {
  * available until run().
  */
 struct dap_ops {
-       /** If the DAP transport isn't SWD, it must be JTAG.  Upper level
-        * code may need to care about the difference in some cases.
-        */
-       bool    is_swd;
-
        /** DP register read. */
        int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
                        uint32_t *data);
@@ -270,13 +284,22 @@ struct dap_ops {
        int (*run)(struct adiv5_dap *dap);
 };
 
+/*
+ * Access Port classes
+ */
+enum ap_class {
+       AP_CLASS_NONE   = 0x00000,  /* No class defined */
+       AP_CLASS_MEM_AP = 0x10000,  /* MEM-AP */
+};
+
 /*
  * Access Port types
  */
 enum ap_type {
-       AP_TYPE_AHB_AP  = 0x01,  /* AHB Memory-AP */
-       AP_TYPE_APB_AP  = 0x02,  /* APB Memory-AP */
-       AP_TYPE_JTAG_AP = 0x10   /* JTAG-AP - JTAG master for controlling other JTAG devices */
+       AP_TYPE_JTAG_AP = 0x0,  /* JTAG-AP - JTAG master for controlling other JTAG devices */
+       AP_TYPE_AHB_AP  = 0x1,  /* AHB Memory-AP */
+       AP_TYPE_APB_AP  = 0x2,  /* APB Memory-AP */
+       AP_TYPE_AXI_AP  = 0x4,  /* AXI Memory-AP */
 };
 
 /**
@@ -432,52 +455,48 @@ static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 /* AP selection applies to future AP transactions */
 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
 
-/* Queued AP transactions */
-int dap_setup_accessport(struct adiv5_dap *swjdp,
-               uint32_t csw, uint32_t tar);
-
-/* Queued MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
+/* Queued MEM-AP memory mapped single word transfers. */
+int mem_ap_read_u32(struct adiv5_ap *ap,
                uint32_t address, uint32_t *value);
-int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
+int mem_ap_write_u32(struct adiv5_ap *ap,
                uint32_t address, uint32_t value);
 
-/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+/* Synchronous MEM-AP memory mapped single word transfers. */
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
                uint32_t address, uint32_t *value);
-int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
                uint32_t address, uint32_t value);
 
-/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
+/* Synchronous MEM-AP memory mapped bus block transfers. */
+int mem_ap_read_buf(struct adiv5_ap *ap,
                uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
+int mem_ap_write_buf(struct adiv5_ap *ap,
                const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 
-/* Synchronous, non-incrementing buffer functions for accessing fifos, with
- * selection of ap */
-int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+/* Synchronous, non-incrementing buffer functions for accessing fifos. */
+int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
                uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
                const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 
 /* Create DAP struct */
 struct adiv5_dap *dap_init(void);
 
 /* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
+int dap_dp_init(struct adiv5_dap *dap);
+int mem_ap_init(struct adiv5_ap *ap);
 
 /* Probe the AP for ROM Table location */
-int dap_get_debugbase(struct adiv5_dap *dap, int ap,
+int dap_get_debugbase(struct adiv5_ap *ap,
                        uint32_t *dbgbase, uint32_t *apid);
 
 /* Probe Access Ports to find a particular type */
 int dap_find_ap(struct adiv5_dap *dap,
                        enum ap_type type_to_find,
-                       uint8_t *ap_num_out);
+                       struct adiv5_ap **ap_out);
 
 /* Lookup CoreSight component */
-int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
+int dap_lookup_cs_component(struct adiv5_ap *ap,
                        uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
 
 struct target;