- change signature for adi_jtag_dp_scan and adi_jtag_dp_scan_u32 to use swjdp_common_...

[openocd.git] / src / target / arm_simulator.c

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 2873a5a65ff9afd2eb901eb4adc7cfec4a131d04..00fbb2d78fdb9bb8fa77a2b14f10a21f505a91ff 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -2,6 +2,9 @@
  *   Copyright (C) 2006 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
+ *   Copyright (C) 2008 by Hongtao Zheng                                   *
+ *   hontor@126.com                                                        *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -21,14 +24,12 @@
 #include "config.h"
 #endif
 
-#include "target.h"
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
 #include "log.h"
 #include "binarybuffer.h"
 
-#include <string.h>
 
 u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
 {
@@ -349,6 +350,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
                else
                {
                        target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32); 
+                       if(instruction.info.b_bl_bx_blx.reg_operand == 15)
+                       {
+                               target += 2 * instruction_size;
+                       }
                }
                
                if (dry_run_pc)
@@ -408,7 +413,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
                u8 carry_out;
                
                Rd = 0x0;
-               Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+               /* ARM_MOV and ARM_MVN does not use Rn */
+               if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
+                       Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+               else
+                       Rn = 0;
+
                shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
 
                /* adjust Rn in case the PC is being read */
@@ -439,6 +449,8 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
                        Rd = shifter_operand;
                else if (instruction.type == ARM_MVN)
                        Rd = ~shifter_operand;
+               else
+                       LOG_WARNING("unhandled instruction type");
                
                if (dry_run_pc)
                {