- reworked image handling to support multiple sections (tested with ihex file contain...
[openocd.git] / src / target / armv4_5.c
index 3eab03354bc6ceb3386f5a74d4aad0ef9fe1a27f..2d73a534d9a294fa0e98b297fb27b51f6a3cf146 100644 (file)
@@ -257,6 +257,13 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
                                armv4_5_target->core_state = ARMV4_5_STATE_ARM; 
                        }
                }
+               
+               if (armv4_5_target->core_mode != (value & 0x1f))
+               {
+                       DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
+                       armv4_5_target->core_mode = value & 0x1f;
+                       armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
+               }
        }
        
        buf_set_u32(reg->value, 0, 32, value);
@@ -442,7 +449,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
        for (i = 0; i < count; i++)
        {
                target_read_u32(target, address, &opcode);
-               evaluate_opcode(opcode, address, &cur_instruction);
+               arm_evaluate_opcode(opcode, address, &cur_instruction);
                command_print(cmd_ctx, "%s", cur_instruction.text);
                address += (thumb) ? 2 : 4;
        }
@@ -598,6 +605,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
                }
        }
        
+       if ((retval != ERROR_TARGET_TIMEOUT) && 
+               (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point))
+       {
+               WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+                       buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); 
+       }
+       
        breakpoint_remove(target, exit_point);
        
        for (i = 0; i < num_mem_params; i++)

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