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Fix make maintainer-clean for out-of-tree builds.
[openocd.git] / src / target / armv4_5.c
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 93dfa8ad34284f139d5ed296db81151cd8239807..eebf866a7ab67ff4cc57d3adf3cf7bbf424af23e 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,21 +27,10 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
-
-#include "arm_disassembler.h"
-
 #include "armv4_5.h"
-
-#include "target.h"
-#include "register.h"
-#include "log.h"
+#include "arm_disassembler.h"
 #include "binarybuffer.h"
-#include "command.h"
 
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
 
 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
 {
@@ -178,7 +167,6 @@ reg_t armv4_5_gdb_dummy_fps_reg =
        "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 };
 
-
 int armv4_5_get_core_reg(reg_t *reg)
 {
        int retval;
@@ -232,7 +220,7 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
                        }
                }
 
-               if (armv4_5_target->core_mode != (value & 0x1f))
+               if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
                {
                        LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
                        armv4_5_target->core_mode = value & 0x1f;
@@ -354,7 +342,7 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
                        output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
                                buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
                }
-               command_print(cmd_ctx, output);
+               command_print(cmd_ctx, "%s", output);
        }
        command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
@@ -397,6 +385,7 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c
 
 int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
+       int retval = ERROR_OK;
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5 = target->arch_info;
        u32 address;
@@ -404,6 +393,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
        int i;
        arm_instruction_t cur_instruction;
        u32 opcode;
+       u16 thumb_opcode;
        int thumb = 0;
 
        if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
@@ -427,8 +417,27 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 
        for (i = 0; i < count; i++)
        {
-               target_read_u32(target, address, &opcode);
-               arm_evaluate_opcode(opcode, address, &cur_instruction);
+               if (thumb)
+               {
+                       if ((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
+                       {
+                               return retval;
+                       }
+                       if ((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
+                       {
+                               return retval;
+                       }
+               }
+               else {
+                       if ((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+                       {
+                               return retval;
+                       }
+                       if ((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+                       {
+                               return retval;
+                       }
+               }
                command_print(cmd_ctx, "%s", cur_instruction.text);
                address += (thumb) ? 2 : 4;
        }
@@ -482,7 +491,10 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
 
-       target_wait_state(target, TARGET_HALTED, timeout_ms);
+       if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+       {
+               return retval;
+       }
        if (target->state != TARGET_HALTED)
        {
                if ((retval=target_halt(target))!=ERROR_OK)
@@ -541,7 +553,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
        for (i = 0; i < num_mem_params; i++)
        {
-               target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+               if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+               {
+                       return retval;
+               }
        }
 
        for (i = 0; i < num_reg_params; i++)
@@ -559,7 +574,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
                        exit(-1);
                }
 
-               armv4_5_set_core_reg(reg, reg_params[i].value);
+               if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
+               {
+                       return retval;
+               }
        }
 
        armv4_5->core_state = armv4_5_algorithm_info->core_state;
@@ -587,16 +605,25 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
                return ERROR_TARGET_FAILURE;
        }
 
-       target_resume(target, 0, entry_point, 1, 1);
-
+       if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+       {
+               return retval;
+       }
+       int retvaltemp;
        retval=run_it(target, exit_point, timeout_ms, arch_info);
 
        breakpoint_remove(target, exit_point);
 
+       if (retval!=ERROR_OK)
+               return retval;
+
        for (i = 0; i < num_mem_params; i++)
        {
                if (mem_params[i].direction != PARAM_OUT)
-                       target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+                       if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+                       {
+                                       retval = retvaltemp;
+                       }
        }
 
        for (i = 0; i < num_reg_params; i++)
@@ -623,10 +650,15 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
        for (i = 0; i <= 16; i++)
        {
-               LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+               u32 regvalue;
+               regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+               if (regvalue != context[i])
+               {
+                       LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+                       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+               }
        }
        buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
        armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
@@ -638,7 +670,6 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
        return retval;
 }
 
-
 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 {
        return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
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