#include "config.h"
#endif
-#include "arm7_9_common.h"
#include "log.h"
-#include "command.h"
#include "armv4_5_mmu.h"
-#include "target.h"
-#include <stdlib.h>
u32 armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap);
-int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
-int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
char* armv4_5_mmu_page_type_names[] =
{
4, 1, (u8*)&first_lvl_descriptor);
first_lvl_descriptor = target_buffer_get_u32(target, (u8*)&first_lvl_descriptor);
- DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
+ LOG_DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
if ((first_lvl_descriptor & 0x3) == 0)
{
*type = -1;
- ERROR("Address translation failure");
+ LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
{
*type = -1;
- ERROR("Address translation failure");
+ LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
4, 1, (u8*)&second_lvl_descriptor);
}
-
+
second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor);
-
- DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
+
+ LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0)
{
*type = -1;
- ERROR("Address translation failure");
+ LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
/* should not happen */
*type = -1;
- ERROR("Address translation failure");
+ LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
/* disable MMU and data (or unified) cache */
armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
-
+
retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
/* reenable MMU / cache */
armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
armv4_5_mmu->armv4_5_cache.i_cache_enabled);
-
+
return retval;
}
u32 cb;
int domain;
u32 ap;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command");
}
return ERROR_OK;
}
-
+
command_print(cmd_ctx, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
va, pa, armv4_5_mmu_page_type_names[type], cb, domain, ap);
- }
-
+ }
+
return ERROR_OK;
}
break;
case ERROR_TARGET_NOT_HALTED:
command_print(cmd_ctx, "error: target must be halted for memory accesses");
- break;
+ break;
case ERROR_TARGET_DATA_ABORT:
command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
break;
{
if (i%8 == 0)
output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size));
-
+
switch (size)
{
case 4:
if ((i % 8 == 7) || (i == count - 1))
{
- command_print(cmd_ctx, output);
+ command_print(cmd_ctx, "%s", output);
output_len = 0;
}
}
free(buffer);
-
+
return ERROR_OK;
}
break;
default:
command_print(cmd_ctx, "error: unknown error");
- }
+ }
return ERROR_OK;
}