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target/riscv: add common magic
[openocd.git] / src / target / armv4_5_mmu.c
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 52756c11e6319885e698cf66cf91ae7100b032d5..b9bc21a8e6b36992ea16750360e77d98fc7f8bf5 100644 (file)
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -1,22 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -25,73 +13,64 @@
 #include "target.h"
 #include "armv4_5_mmu.h"
 
-
-int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap, uint32_t *val)
+int armv4_5_mmu_translate_va(struct target *target,
+               struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
 {
        uint32_t first_lvl_descriptor = 0x0;
        uint32_t second_lvl_descriptor = 0x0;
-       uint32_t ttb = armv4_5_mmu->get_ttb(target);
+       uint32_t ttb;
        int retval;
+       retval = armv4_5_mmu->get_ttb(target, &ttb);
+       if (retval != ERROR_OK)
+               return retval;
 
        retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
                (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
-               4, 1, (uint8_t*)&first_lvl_descriptor);
+               4, 1, (uint8_t *)&first_lvl_descriptor);
        if (retval != ERROR_OK)
-         return retval;
-       first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
+               return retval;
+       first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
 
        LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
 
-       if ((first_lvl_descriptor & 0x3) == 0)
-       {
+       if ((first_lvl_descriptor & 0x3) == 0) {
                LOG_ERROR("Address translation failure");
                return ERROR_TARGET_TRANSLATION_FAULT;
        }
 
-       if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
-       {
+       if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) {
                LOG_ERROR("Address translation failure");
                return ERROR_TARGET_TRANSLATION_FAULT;
        }
 
-       /* domain is always specified in bits 8-5 */
-       *domain = (first_lvl_descriptor & 0x1e0) >> 5;
-
-       if ((first_lvl_descriptor & 0x3) == 2)
-       {
+       if ((first_lvl_descriptor & 0x3) == 2) {
                /* section descriptor */
-               *type = ARMV4_5_SECTION;
                *cb = (first_lvl_descriptor & 0xc) >> 2;
-               *ap = (first_lvl_descriptor & 0xc00) >> 10;
                *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
                return ERROR_OK;
        }
 
-       if ((first_lvl_descriptor & 0x3) == 1)
-       {
+       if ((first_lvl_descriptor & 0x3) == 1) {
                /* coarse page table */
                retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
                        (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
-                       4, 1, (uint8_t*)&second_lvl_descriptor);
+                       4, 1, (uint8_t *)&second_lvl_descriptor);
                if (retval != ERROR_OK)
                        return retval;
-       }
-       else if ((first_lvl_descriptor & 0x3) == 3)
-       {
+       } else if ((first_lvl_descriptor & 0x3) == 3) {
                /* fine page table */
                retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
                        (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
-                       4, 1, (uint8_t*)&second_lvl_descriptor);
+                       4, 1, (uint8_t *)&second_lvl_descriptor);
                if (retval != ERROR_OK)
                        return retval;
        }
 
-       second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
+       second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
 
        LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
 
-       if ((second_lvl_descriptor & 0x3) == 0)
-       {
+       if ((second_lvl_descriptor & 0x3) == 0) {
                LOG_ERROR("Address translation failure");
                return ERROR_TARGET_TRANSLATION_FAULT;
        }
@@ -99,29 +78,20 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
        /* cacheable/bufferable is always specified in bits 3-2 */
        *cb = (second_lvl_descriptor & 0xc) >> 2;
 
-       if ((second_lvl_descriptor & 0x3) == 1)
-       {
+       if ((second_lvl_descriptor & 0x3) == 1) {
                /* large page descriptor */
-               *type = ARMV4_5_LARGE_PAGE;
-               *ap = (second_lvl_descriptor & 0xff0) >> 4;
                *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
                return ERROR_OK;
        }
 
-       if ((second_lvl_descriptor & 0x3) == 2)
-       {
+       if ((second_lvl_descriptor & 0x3) == 2) {
                /* small page descriptor */
-               *type = ARMV4_5_SMALL_PAGE;
-               *ap = (second_lvl_descriptor & 0xff0) >> 4;
                *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
                return ERROR_OK;
        }
 
-       if ((second_lvl_descriptor & 0x3) == 3)
-       {
+       if ((second_lvl_descriptor & 0x3) == 3) {
                /* tiny page descriptor */
-               *type = ARMV4_5_TINY_PAGE;
-               *ap = (second_lvl_descriptor & 0x30) >> 4;
                *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
                return ERROR_OK;
        }
@@ -131,7 +101,9 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
        return ERROR_TARGET_TRANSLATION_FAULT;
 }
 
-int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_read_physical(struct target *target,
+               struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
+               uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
 
@@ -139,19 +111,27 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
                return ERROR_TARGET_NOT_HALTED;
 
        /* disable MMU and data (or unified) cache */
-       armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       if (retval != ERROR_OK)
+               return retval;
 
        retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* reenable MMU / cache */
-       armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+       retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
                armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
                armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+       if (retval != ERROR_OK)
+               return retval;
 
        return retval;
 }
 
-int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_write_physical(struct target *target,
+               struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
 
@@ -159,14 +139,20 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common
                return ERROR_TARGET_NOT_HALTED;
 
        /* disable MMU and data (or unified) cache */
-       armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       if (retval != ERROR_OK)
+               return retval;
 
        retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* reenable MMU / cache */
-       armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+       retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
                armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
                armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+       if (retval != ERROR_OK)
+               return retval;
 
        return retval;
 }
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