* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
armv7a->armv7a_mmu.ttbr_mask[0],
armv7a->armv7a_mmu.ttbr_mask[1]);
- /* FIXME: default is hard coded LINUX border */
- armv7a->armv7a_mmu.os_border = 0xc0000000;
- if (ttbcr_n != 0) {
- LOG_INFO("SVC access above %" PRIx32,
- armv7a->armv7a_mmu.ttbr_range[0] + 1);
- armv7a->armv7a_mmu.os_border = armv7a->armv7a_mmu.ttbr_range[0] + 1;
- }
done:
dpm->finish(dpm);
return retval;
}
-/* method adapted to cortex A : reused arm v4 v5 method*/
+/* method adapted to Cortex-A : reused ARM v4 v5 method */
int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
uint32_t first_lvl_descriptor = 0x0;
break;
case 7:
LOG_INFO("inner: Write-Back, no Write-Allocate");
-
+ break;
default:
LOG_INFO("inner: %" PRIx32 " ???", INNER);
}
return retval;
}
-static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
- struct armv7a_cache_common *armv7a_cache)
-{
- int cl;
-
- if (armv7a_cache->info == -1) {
- command_print(cmd_ctx, "cache not yet identified");
- return ERROR_OK;
- }
-
- for (cl = 0; cl < armv7a_cache->loc; cl++) {
- struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
-
- if (arch->ctype & 1) {
- command_print(cmd_ctx,
- "L%d I-Cache: linelen %" PRIi32
- ", associativity %" PRIi32
- ", nsets %" PRIi32
- ", cachesize %" PRId32 " KBytes",
- cl+1,
- arch->i_size.linelen,
- arch->i_size.associativity,
- arch->i_size.nsets,
- arch->i_size.cachesize);
- }
-
- if (arch->ctype >= 2) {
- command_print(cmd_ctx,
- "L%d D-Cache: linelen %" PRIi32
- ", associativity %" PRIi32
- ", nsets %" PRIi32
- ", cachesize %" PRId32 " KBytes",
- cl+1,
- arch->d_u_size.linelen,
- arch->d_u_size.associativity,
- arch->d_u_size.nsets,
- arch->d_u_size.cachesize);
- }
- }
-
- return ERROR_OK;
-}
-
/* FIXME: remove it */
static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
{
struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
(armv7a_cache->outer_cache);
+ int cl;
+
if (armv7a_cache->info == -1) {
command_print(cmd_ctx, "cache not yet identified");
return ERROR_OK;
}
- if (armv7a_cache->display_cache_info)
- armv7a_cache->display_cache_info(cmd_ctx, armv7a_cache);
+ for (cl = 0; cl < armv7a_cache->loc; cl++) {
+ struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
+
+ if (arch->ctype & 1) {
+ command_print(cmd_ctx,
+ "L%d I-Cache: linelen %" PRIi32
+ ", associativity %" PRIi32
+ ", nsets %" PRIi32
+ ", cachesize %" PRId32 " KBytes",
+ cl+1,
+ arch->i_size.linelen,
+ arch->i_size.associativity,
+ arch->i_size.nsets,
+ arch->i_size.cachesize);
+ }
+
+ if (arch->ctype >= 2) {
+ command_print(cmd_ctx,
+ "L%d D-Cache: linelen %" PRIi32
+ ", associativity %" PRIi32
+ ", nsets %" PRIi32
+ ", cachesize %" PRId32 " KBytes",
+ cl+1,
+ arch->d_u_size.linelen,
+ arch->d_u_size.associativity,
+ arch->d_u_size.nsets,
+ arch->d_u_size.cachesize);
+ }
+ }
+
if (l2x_cache != NULL)
command_print(cmd_ctx, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
l2x_cache->base, l2x_cache->way);
/* if no l2 cache initialize l1 data cache flush function function */
if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) {
- armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
- armv7a_handle_inner_cache_info_command;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
armv7a_cache_auto_flush_all_data;
}
}
+static int armv7a_setup_semihosting(struct target *target, int enable)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ uint32_t vcr;
+ int ret;
+
+ ret = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_VCR,
+ &vcr);
+ if (ret < 0) {
+ LOG_ERROR("Failed to read VCR register\n");
+ return ret;
+ }
+
+ if (enable)
+ vcr |= DBG_VCR_SVC_MASK;
+ else
+ vcr &= ~DBG_VCR_SVC_MASK;
+
+ ret = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_VCR,
+ vcr);
+ if (ret < 0)
+ LOG_ERROR("Failed to write VCR register\n");
+
+ return ret;
+}
+
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
{
struct arm *arm = &armv7a->arm;
arm->arch_info = armv7a;
target->arch_info = &armv7a->arm;
+ arm->setup_semihosting = armv7a_setup_semihosting;
/* target is useful in all function arm v4 5 compatible */
armv7a->arm.target = target;
armv7a->arm.common_magic = ARM_COMMON_MAGIC;
armv7a->armv7a_mmu.armv7a_cache.info = -1;
armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
- armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1;
return ERROR_OK;
}