* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
/* check that cache data is on at target halt */
if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
- LOG_DEBUG("l1 data cache is not enabled");
+ LOG_DEBUG("data cache is not enabled");
return ERROR_TARGET_INVALID;
}
/* check that cache data is on at target halt */
if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
- LOG_DEBUG("l1 data cache is not enabled");
+ LOG_DEBUG("instruction cache is not enabled");
return ERROR_TARGET_INVALID;
}
}
-static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
+int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
uint32_t size)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
- uint32_t i, linelen = armv7a_cache->dminline;
+ uint32_t linelen = armv7a_cache->dminline;
+ uint32_t va_line, va_end;
int retval;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
goto done;
- for (i = 0; i < size; i += linelen) {
- uint32_t offs = virt + i;
+ va_line = virt & (-linelen);
+ va_end = virt + size;
+
+ /* handle unaligned start */
+ if (virt != va_line) {
+ /* DCCIMVAC */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
+ if (retval != ERROR_OK)
+ goto done;
+ va_line += linelen;
+ }
- /* DCIMVAC - Clean and invalidate data cache line by VA to PoC. */
+ /* handle unaligned end */
+ if ((va_end & (linelen-1)) != 0) {
+ va_end &= (-linelen);
+ /* DCCIMVAC */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 6, 1), offs);
+ ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_end);
if (retval != ERROR_OK)
goto done;
}
+
+ while (va_line < va_end) {
+ /* DCIMVAC - Invalidate data cache line by VA to PoC. */
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
+ if (retval != ERROR_OK)
+ goto done;
+ va_line += linelen;
+ }
+
+ dpm->finish(dpm);
return retval;
done:
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
- uint32_t i, linelen = armv7a_cache->dminline;
+ uint32_t linelen = armv7a_cache->dminline;
+ uint32_t va_line, va_end;
int retval;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
goto done;
- for (i = 0; i < size; i += linelen) {
- uint32_t offs = virt + i;
+ va_line = virt & (-linelen);
+ va_end = virt + size;
+ while (va_line < va_end) {
/* DCCMVAC - Data Cache Clean by MVA to PoC */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 10, 1), offs);
+ ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
if (retval != ERROR_OK)
goto done;
+ va_line += linelen;
}
+
+ dpm->finish(dpm);
return retval;
done:
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
- uint32_t i, linelen = armv7a_cache->dminline;
+ uint32_t linelen = armv7a_cache->dminline;
+ uint32_t va_line, va_end;
int retval;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
goto done;
- for (i = 0; i < size; i += linelen) {
- uint32_t offs = virt + i;
+ va_line = virt & (-linelen);
+ va_end = virt + size;
+ while (va_line < va_end) {
/* DCCIMVAC */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 14, 1), offs);
+ ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
if (retval != ERROR_OK)
goto done;
+ va_line += linelen;
}
+
+ dpm->finish(dpm);
return retval;
done: