#include "config.h"
#endif
-#include "replacements.h"
-
#include "armv7m.h"
-#include "register.h"
-#include "target.h"
-#include "log.h"
-#include "jtag.h"
-#include "arm_jtag.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
/* ARMV7M is always in thumb mode, try to make GDB understand this
* if it does not support this arch */
- armv7m->core_cache->reg_list[15].value[0] |= 1;
+ *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
#else
(*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
#endif
u32 pc;
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
- sequence to write register values to the processor and the read them back */
+ * sequence to write register values to the processor and the read them back */
if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
{
return retval;
}
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
- // If the target fails to halt due to the breakpoint, force a halt
+ /* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
if ((retval=target_halt(target))!=ERROR_OK)
return ERROR_TARGET_TIMEOUT;
}
-
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (pc != exit_point)
{
armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
enum armv7m_mode core_mode = armv7m->core_mode;
int retval = ERROR_OK;
- u32 pc;
int i;
u32 context[ARMV7NUMCOREREGS];
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
- u32 regvalue;
+// u32 regvalue;
if (!reg)
{
exit(-1);
}
- regvalue = buf_get_u32(reg_params[i].value, 0, 32);
+// regvalue = buf_get_u32(reg_params[i].value, 0, 32);
armv7m_set_core_reg(reg, reg_params[i].value);
}
for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
{
- LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
- buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
- armv7m->core_cache->reg_list[i].valid = 1;
- armv7m->core_cache->reg_list[i].dirty = 1;
+ u32 regvalue;
+ regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
+ if (regvalue != context[i])
+ {
+ LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
+ buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
+ armv7m->core_cache->reg_list[i].valid = 1;
+ armv7m->core_cache->reg_list[i].dirty = 1;
+ }
}
armv7m->core_mode = core_mode;
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
+ command_t *arm_adi_v5_dap_cmd;
+
+ arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]");
+
return ERROR_OK;
}
0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
};
- int i;
+ u32 i;
if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
{
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
+ if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
{
LOG_ERROR("error executing cortex_m3 crc algorithm");
reg_param_t reg_params[3];
armv7m_algorithm_t armv7m_info;
int retval;
- int i;
+ u32 i;
u16 erase_check_code[] =
{
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
- if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
+ if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
{
destroy_reg_param(®_params[0]);
return ERROR_OK;
}
+
+/********************************************************************************************************************
+* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apselsave, baseaddr;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8x", baseaddr);
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+
+/********************************************************************************************************************
+* Return the debug ap id in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apselsave, apid;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8x", apid);
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apid;
+ int retval;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
+
+ return retval;
+}
+
+int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 memaccess_tck;
+
+ memaccess_tck = swjdp->memaccess_tck;
+ if (argc > 0)
+ {
+ memaccess_tck = strtoul(args[0], NULL, 0);
+ }
+
+ swjdp->memaccess_tck = memaccess_tck;
+ command_print(cmd_ctx, "memory bus access delay set to %i tck", swjdp->memaccess_tck);
+
+ return ERROR_OK;
+}
+
+int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ int retval;
+ u32 apsel;
+
+ apsel = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ retval = dap_info_command(cmd_ctx, swjdp, apsel);
+
+ return retval;
+}
+
Code Review / openocd.git / blobdiff