#include "target.h"
#include "target_type.h"
-#define __unused __attribute__((unused))
-
static const char * const armv8_state_strings[] = {
"AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
};
const char *name;
unsigned psr;
} armv8_mode_data[] = {
- /* These special modes are currently only supported
- * by ARMv6M and ARMv7M profiles */
{
.name = "USR",
.psr = ARM_MODE_USR,
return "UNRECOGNIZED";
}
-int armv8_mode_to_number(enum arm_mode mode)
-{
- switch (mode) {
- case ARM_MODE_ANY:
- /* map MODE_ANY to user mode */
- case ARM_MODE_USR:
- return 0;
- case ARM_MODE_FIQ:
- return 1;
- case ARM_MODE_IRQ:
- return 2;
- case ARM_MODE_SVC:
- return 3;
- case ARM_MODE_ABT:
- return 4;
- case ARM_MODE_UND:
- return 5;
- case ARM_MODE_SYS:
- return 6;
- case ARM_MODE_MON:
- return 7;
- case ARMV8_64_EL0T:
- return 8;
- case ARMV8_64_EL1T:
- return 9;
- case ARMV8_64_EL1H:
- return 10;
- case ARMV8_64_EL2T:
- return 11;
- case ARMV8_64_EL2H:
- return 12;
- case ARMV8_64_EL3T:
- return 13;
- case ARMV8_64_EL3H:
- return 14;
-
- default:
- LOG_ERROR("invalid mode value encountered %d", mode);
- return -1;
- }
-}
-
static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regval)
{
struct arm_dpm *dpm = &armv8->dpm;
break;
case ARMV8_SP:
retval = dpm->instr_write_data_dcc(dpm,
- ARMV4_5_MRC(14, 0, 13, 0, 5, 0),
- value);
+ ARMV4_5_MRC(14, 0, 13, 0, 5, 0), value);
break;
case ARMV8_PC:/* PC
* read r0 from DCC; then "MOV pc, r0" */
LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
armv8->cluster_id,
armv8->cpu_id,
- armv8->multi_processor_system == 0 ? "multi core" : "mono core");
-
+ armv8->multi_processor_system == 0 ? "multi core" : "single core");
} else
- LOG_ERROR("mpdir not in multiprocessor format");
+ LOG_ERROR("mpidr not in multiprocessor format");
done:
dpm->finish(dpm);
/* Older ARMs won't have the J bit */
enum arm_state state = 0xFF;
- if (((cpsr & 0x10) >> 4) == 0) {
- state = ARM_STATE_AARCH64;
- } else {
+ if ((cpsr & 0x10) != 0) {
+ /* Aarch32 state */
if (cpsr & (1 << 5)) { /* T */
if (cpsr & (1 << 24)) { /* J */
LOG_WARNING("ThumbEE -- incomplete support");
} else
state = ARM_STATE_ARM;
}
+ } else {
+ /* Aarch64 state */
+ state = ARM_STATE_AARCH64;
}
+
arm->core_state = state;
- if (arm->core_state == ARM_STATE_AARCH64)
- arm->core_mode = (mode << 4) | 0xf;
- else
- arm->core_mode = mode;
+ arm->core_mode = mode;
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
armv8_mode_name(arm->core_mode),
/* (void) */ dpm->finish(dpm);
}
-static void armv8_show_fault_registers(struct target *target)
+static __attribute__((unused)) void armv8_show_fault_registers(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
return ret;
}
-static __unused int armv8_read_ttbcr32(struct target *target)
+static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
return retval;
}
-static __unused int armv8_read_ttbcr(struct target *target)
+static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
dpm->finish(dpm);
- if (retval != ERROR_OK)
- return retval;
-
if (retval != ERROR_OK)
return retval;
struct reg *reg64;
int retval;
- LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
- reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
-
/* get the corresponding Aarch64 register */
reg64 = cache->reg_list + armv8_reg->num;
if (reg64->valid) {
return ERROR_OK;
}
- retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
+ retval = arm->read_core_reg(target, reg64, armv8_reg->num, arm->core_mode);
if (retval == ERROR_OK)
reg->valid = reg64->valid;
struct reg *reg64 = cache->reg_list + armv8_reg->num;
uint32_t value = buf_get_u32(buf, 0, 32);
- if (target->state != TARGET_HALTED)
- return ERROR_TARGET_NOT_HALTED;
-
if (reg64 == arm->cpsr) {
armv8_set_cpsr(arm, value);
} else {
if (arm->core_state == ARM_STATE_AARCH64) {
- LOG_DEBUG("Creating Aarch64 register list");
+ LOG_DEBUG("Creating Aarch64 register list for target %s", target_name(target));
switch (reg_class) {
case REG_CLASS_GENERAL:
} else {
struct reg_cache *cache32 = arm->core_cache->next;
- LOG_DEBUG("Creating Aarch32 register list");
+ LOG_DEBUG("Creating Aarch32 register list for target %s", target_name(target));
switch (reg_class) {
case REG_CLASS_GENERAL:
}
}
}
+
+int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value)
+{
+ uint32_t tmp;
+
+ /* Read register */
+ int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + reg, &tmp);
+ if (ERROR_OK != retval)
+ return retval;
+
+ /* clear bitfield */
+ tmp &= ~mask;
+ /* put new value */
+ tmp |= value & mask;
+
+ /* write new value */
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + reg, tmp);
+ return retval;
+}