retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
/* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *lvalue = value_r1;
- *lvalue = ((*lvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *lvalue = value_r1;
+ *lvalue = ((*lvalue) << 32) | value_r0;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *hvalue = value_r1;
- *hvalue = ((*hvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *hvalue = value_r1;
+ *hvalue = ((*hvalue) << 32) | value_r0;
break;
default:
retval = ERROR_FAIL;
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
/* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);
+ if (retval != ERROR_OK)
+ return retval;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);