/* TODO */
}
+static uint8_t armv8_pa_size(uint32_t ps)
+{
+ uint8_t ret = 0;
+ switch (ps) {
+ case 0:
+ ret = 32;
+ break;
+ case 1:
+ ret = 36;
+ break;
+ case 2:
+ ret = 40;
+ break;
+ case 3:
+ ret = 42;
+ break;
+ case 4:
+ ret = 44;
+ break;
+ case 5:
+ ret = 48;
+ break;
+ default:
+ LOG_INFO("Unknow physicall address size");
+ break;
+ }
+ return ret;
+}
+
static int armv8_read_ttbcr(struct target *target)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
+ struct arm *arm = &armv8->arm;
uint32_t ttbcr;
+ uint64_t ttbcr_64;
+
int retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
- /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
- &ttbcr);
+
+ /* claaer ttrr1_used and ttbr0_mask */
+ memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
+ memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
+
+ switch (arm->core_mode) {
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL3, 0),
+ &ttbcr);
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ armv8->va_size = 64 - (ttbcr & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+ armv8->page_size = (ttbcr >> 14) & 3;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL2, 0),
+ &ttbcr);
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ armv8->va_size = 64 - (ttbcr & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
+ armv8->page_size = (ttbcr >> 14) & 3;
+ break;
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TCR_EL1, 0),
+ &ttbcr_64);
+ armv8->va_size = 64 - (ttbcr_64 & 0x3F);
+ armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
+ armv8->page_size = (ttbcr_64 >> 14) & 3;
+ armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
+ armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
+ retval += dpm->instr_read_data_r0_64(dpm,
+ ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
+ &armv8->ttbr_base);
+ if (retval != ERROR_OK)
+ goto done;
+ break;
+ default:
+ LOG_ERROR("unknow core state");
+ retval = ERROR_FAIL;
+ break;
+ }
if (retval != ERROR_OK)
goto done;
- armv8->armv8_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
- armv8->armv8_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
+
#if 0
- LOG_INFO("ttb1 %s ,ttb0_mask %x",
+ LOG_INFO("ttb1 %s ,ttb0_mask %llx",
armv8->armv8_mmu.ttbr1_used ? "used" : "not used",
armv8->armv8_mmu.ttbr0_mask);
#endif
if (armv8->armv8_mmu.ttbr1_used == 1) {
- LOG_INFO("SVC access above %" PRIx32,
- (uint32_t)(0xffffffff & armv8->armv8_mmu.ttbr0_mask));
- armv8->armv8_mmu.os_border = 0xffffffff & armv8->armv8_mmu.ttbr0_mask;
+ LOG_INFO("TTBR0 access above %" PRIx64,
+ (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
+ armv8->armv8_mmu.os_border = armv8->armv8_mmu.ttbr0_mask;
} else {
/* fix me , default is hard coded LINUX border */
armv8->armv8_mmu.os_border = 0xc0000000;
return retval;
}
+static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
+{
+ LOG_ERROR("4K page Address translation need to add");
+ return ERROR_FAIL;
+}
+
/* method adapted to cortex A : reused arm v4 v5 method*/
int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
- uint32_t first_lvl_descriptor = 0x0;
- uint32_t second_lvl_descriptor = 0x0;
- int retval;
+ int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
- uint32_t ttb = 0; /* default ttb0 */
- if (armv8->armv8_mmu.ttbr1_used == -1)
- armv8_read_ttbcr(target);
- if ((armv8->armv8_mmu.ttbr1_used) &&
- (va > (0xffffffff & armv8->armv8_mmu.ttbr0_mask))) {
- /* select ttb 1 */
- ttb = 1;
- }
+
retval = dpm->prepare(dpm);
+ retval += armv8_read_ttbcr(target);
if (retval != ERROR_OK)
goto done;
-
- /* MRC p15,0,<Rt>,c2,c0,ttb */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
- &ttb);
- if (retval != ERROR_OK)
- return retval;
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
- 4, 1, (uint8_t *)&first_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &first_lvl_descriptor);
- /* reuse armv4_5 piece of code, specific armv8 changes may come later */
- LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
- if ((first_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
-
- if ((first_lvl_descriptor & 0x3) == 2) {
- /* section descriptor */
- *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
- return ERROR_OK;
- }
-
- if ((first_lvl_descriptor & 0x3) == 1) {
- /* coarse page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- } else if ((first_lvl_descriptor & 0x3) == 3) {
- /* fine page table */
- retval = armv8->armv8_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- }
-
- second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
- &second_lvl_descriptor);
-
- LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
- if ((second_lvl_descriptor & 0x3) == 0) {
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
- }
-
- if ((second_lvl_descriptor & 0x3) == 1) {
- /* large page descriptor */
- *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 2) {
- /* small page descriptor */
- *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 3) {
- *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
- return ERROR_OK;
- }
-
- /* should not happen */
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
+ if (armv8->page_size == 0)
+ return armv8_4K_translate(target, va, val);
done:
- return retval;
+ dpm->finish(dpm);
+ return ERROR_FAIL;
}
/* V8 method VA TO PA */
int armv8_identify_cache(struct target *target)
{
- /* read cache descriptor */
+ /* read cache descriptor */
int retval = ERROR_FAIL;
struct armv8_common *armv8 = target_to_armv8(target);
struct arm_dpm *dpm = armv8->arm.dpm;
uint32_t cache_selected, clidr;
uint32_t cache_i_reg, cache_d_reg;
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
- if (!armv8->is_armv7r)
- armv8_read_ttbcr(target);
+ armv8_read_ttbcr(target);
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
- /* retrieve CLIDR
- * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
+ /* retrieve CLIDR
+ * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
+ ARMV8_MRS(SYSTEM_CLIDR, 0),
&clidr);
if (retval != ERROR_OK)
goto done;
LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
if ((clidr / 2) > 1) {
/* FIXME not supported present in cortex A8 and later */
- /* in cortex A7, A15 */
+ /* in cortex A7, A15 */
LOG_ERROR("cache l2 present :not supported");
}
- /* retrieve selected cache
- * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
+ /* retrieve selected cache*/
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
&cache_selected);
if (retval != ERROR_OK)
goto done;
- retval = armv8->arm.mrc(target, 15,
- 2, 0, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- &cache_selected);
- if (retval != ERROR_OK)
- goto done;
+
/* select instruction cache
- * MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
- * [0] : 1 instruction cache selection , 0 data cache selection */
+ * [0] : 1 instruction cache selection , 0 data cache selection */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
1);
if (retval != ERROR_OK)
goto done;
/* read CCSIDR
* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
- * [2:0] line size 001 eight word per line
+ * [2:0] line size 001 eight word per line
* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_i_reg);
if (retval != ERROR_OK)
goto done;
- /* select data cache*/
+ /* select data cache*/
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
0);
if (retval != ERROR_OK)
goto done;
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_d_reg);
if (retval != ERROR_OK)
goto done;
- /* restore selected cache */
+ /* restore selected cache */
dpm->instr_write_data_r0(dpm,
- ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
+ ARMV8_MRS(SYSTEM_CSSELR, 0),
cache_selected);
if (retval != ERROR_OK)
Code Review / openocd.git / blobdiff