aarch64: remove armv7-a virt-to-phys code

[openocd.git] / src / target / armv8.h

diff --git a/src/target/armv8.h b/src/target/armv8.h
index 9c6ccce470213483c1dfc289bc826bb9f02e965e..884d39a3ac9fa33218c9925c495f61e908bacc1e 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -113,7 +113,7 @@ struct armv8_cache_common {
 struct armv8_mmu_common {
        /* following field mmu working way */
        int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
-       uint32_t ttbr0_mask;/*  masked to be used  */
+       uint64_t ttbr0_mask;/*  masked to be used  */
        uint32_t os_border;
 
        int (*read_physical_memory)(struct target *target, target_addr_t address,
@@ -141,6 +141,12 @@ struct armv8_common {
        uint8_t cpu_id;
        bool is_armv7r;
 
+       /* armv8 aarch64 need below information for page translation */
+       uint8_t va_size;
+       uint8_t pa_size;
+       uint32_t page_size;
+       uint64_t ttbr_base;
+
        /* cache specific to V7 Memory Management Unit compatible with v4_5*/
        struct armv8_mmu_common armv8_mmu;
 
@@ -222,6 +228,18 @@ target_to_armv8(struct target *target)
 #define CTI_GATE                       0x140
 #define CTI_UNLOCK                     0xFB0
 
+#define PAGE_SIZE_4KB                          0x1000
+#define PAGE_SIZE_4KB_LEVEL0_BITS      39
+#define PAGE_SIZE_4KB_LEVEL1_BITS      30
+#define PAGE_SIZE_4KB_LEVEL2_BITS      21
+#define PAGE_SIZE_4KB_LEVEL3_BITS      12
+
+#define PAGE_SIZE_4KB_LEVEL0_MASK      ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
+#define PAGE_SIZE_4KB_LEVEL1_MASK      ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
+#define PAGE_SIZE_4KB_LEVEL2_MASK      ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
+#define PAGE_SIZE_4KB_LEVEL3_MASK      ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
+
+#define PAGE_SIZE_4KB_TRBBASE_MASK     0xFFFFFFFFF000
 
 int armv8_arch_state(struct target *target);
 int armv8_identify_cache(struct target *target);