return ERROR_TARGET_INVALID;
}
-static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
+static int armv8_cache_d_inner_flush_level(struct armv8_common *armv8, struct armv8_cachesize *size, int cl)
{
+ struct arm_dpm *dpm = armv8->arm.dpm;
int retval = ERROR_OK;
int32_t c_way, c_index = size->index;
* line by Set/Way.
*/
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_SYS(SYSTEM_DCCISW, 0), value);
+ armv8_opcode(armv8, ARMV8_OPC_DCCISW), value);
if (retval != ERROR_OK)
goto done;
c_way -= 1;
if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
continue;
- armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
+ armv8_cache_d_inner_flush_level(armv8, &cache->arch[cl].d_u_size, cl);
}
retval = dpm->finish(dpm);
/* DC CIVAC */
/* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
retval = dpm->instr_write_data_r0_64(dpm,
- ARMV8_SYS(SYSTEM_DCCIVAC, 0), va_line);
+ armv8_opcode(armv8, ARMV8_OPC_DCCIVAC), va_line);
if (retval != ERROR_OK)
goto done;
va_line += linelen;
while (va_line < va_end) {
/* IC IVAU - Invalidate instruction cache by VA to PoU. */
retval = dpm->instr_write_data_r0_64(dpm,
- ARMV8_SYS(SYSTEM_ICIVAU, 0), va_line);
+ armv8_opcode(armv8, ARMV8_OPC_ICIVAU), va_line);
if (retval != ERROR_OK)
goto done;
va_line += linelen;
static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
{
+ struct armv8_common *armv8 = dpm->arm->arch_info;
int retval = ERROR_OK;
/* select cache level */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
+ armv8_opcode(armv8, WRITE_REG_CSSELR),
(cl << 1) | (ct == 1 ? 1 : 0));
if (retval != ERROR_OK)
goto done;
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(SYSTEM_CCSIDR, 0),
+ armv8_opcode(armv8, READ_REG_CCSIDR),
cache_reg);
done:
return retval;
{
/* read cache descriptor */
int retval = ERROR_FAIL;
+ struct arm *arm = &armv8->arm;
struct arm_dpm *dpm = armv8->arm.dpm;
uint32_t csselr, clidr, ctr;
uint32_t cache_reg;
if (retval != ERROR_OK)
goto done;
+ /* check if we're in an unprivileged mode */
+ if (armv8_curel_from_core_mode(arm->core_mode) < SYSTEM_CUREL_EL1) {
+ retval = armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
/* retrieve CTR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CTR), &ctr);
if (retval != ERROR_OK)
goto done;
ctr, cache->iminline, cache->dminline);
/* retrieve CLIDR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0), &clidr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
if (retval != ERROR_OK)
goto done;
/* retrieve selected cache for later restore
* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
- retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0), &csselr);
+ retval = dpm->instr_read_data_r0(dpm,
+ armv8_opcode(armv8, READ_REG_CSSELR), &csselr);
if (retval != ERROR_OK)
goto done;
}
/* restore selected cache */
- dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
+ dpm->instr_write_data_r0(dpm,
+ armv8_opcode(armv8, WRITE_REG_CSSELR), csselr);
if (retval != ERROR_OK)
goto done;
}
done:
+ armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
dpm->finish(dpm);
return retval;