target/cortex_m: prevent asserting reset if examine is deferred

[openocd.git] / src / target / armv8_opcodes.h

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 8c213ef4dde0bfe1b5a8acbc1b911081642ecced..ddb0f9b0738194f6f45b24d0a53fb4af1b54e7d8 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -1,17 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /*
- * Copyright (C) 2015 by pierrr kuo
- * vichy.kuo@gmail.com
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
+ * Copyright (C) 2015 by pierrr kuo <vichy.kuo@gmail.com>
  */
+
 #ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
 #define OPENOCD_TARGET_ARMV8_OPCODES_H
 
@@ -146,9 +138,9 @@
        (0xd500401f | ((op1) << 16)  | ((crm) << 8) | ((op2) << 5))
 
 #define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
-#define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
+#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
 #define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
-#define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
+#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
 
 #define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
 #define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
@@ -163,6 +155,7 @@
 #define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
 #define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
 #define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
+#define ARMV8_LDRD_IP(rd, rn) (0xf8408400 | (rn << 5) | rd)
 
 #define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
 #define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
@@ -171,6 +164,7 @@
 #define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
 #define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
 #define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)
+#define ARMV8_STRD_IP(rd, rn) (0xf8008400 | (rn << 5) | rd)
 
 #define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12))
 #define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12))
@@ -208,9 +202,11 @@ enum armv8_opcode {
        ARMV8_OPC_STRB_IP,
        ARMV8_OPC_STRH_IP,
        ARMV8_OPC_STRW_IP,
+       ARMV8_OPC_STRD_IP,
        ARMV8_OPC_LDRB_IP,
        ARMV8_OPC_LDRH_IP,
        ARMV8_OPC_LDRW_IP,
+       ARMV8_OPC_LDRD_IP,
        ARMV8_OPC_NUM,
 };