ARM7TDMI uses the new inheritance/nesting scheme

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 821d7194eb63d1613ee02398e80d78c85fc58081..29fffaebb2154944e2225ea4dccb3c000731ff56 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -70,6 +70,11 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target,
 int cortex_a8_assert_reset(target_t *target);
 int cortex_a8_deassert_reset(target_t *target);
 
+static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1,
+               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1,
+               uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+
 target_type_t cortexa8_target =
 {
        .name = "cortex_a8",
@@ -106,7 +111,8 @@ target_type_t cortexa8_target =
        .target_create = cortex_a8_target_create,
        .init_target = cortex_a8_init_target,
        .examine = cortex_a8_examine,
-       .quit = NULL
+       .mrc = cortex_a8_mrc,
+       .mcr = cortex_a8_mcr,
 };
 
 /*
@@ -140,13 +146,13 @@ int cortex_a8_init_debug_access(target_t *target)
        /* Clear Sticky Power Down status Bit in PRSR to enable access to
           the registers in the Core Power Domain */
        retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
-       /* Enabling of instruction execution in debug mode is done in debug_entry code */ 
-       
+       /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
        /* Resync breakpoint registers */
-       
+
        /* Since this is likley called from init or reset, update targtet state information*/
        cortex_a8_poll(target);
-       
+
        return retval;
 }
 
@@ -236,11 +242,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
        uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
        int retval;
+       uint32_t dscr;
+
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
+       LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
+
+       /* Check that DCCRX is not full */
+       retval = mem_ap_read_atomic_u32(swjdp,
+                               armv7a->debug_base + CPUDBG_DSCR, &dscr);
+       if (dscr & (1 << DSCR_DTR_RX_FULL))
+       {
+               LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+               /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+       }
+
        retval = mem_ap_write_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DTRRX, value);
        /* Move DTRRX to r0 */
@@ -262,6 +282,28 @@ int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
        return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
 }
 
+static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+       if (cpnum!=15)
+       {
+               LOG_ERROR("Only cp15 is supported");
+               return ERROR_FAIL;
+       }
+       return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+       if (cpnum!=15)
+       {
+               LOG_ERROR("Only cp15 is supported");
+               return ERROR_FAIL;
+       }
+       return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+
+
 int cortex_a8_dap_read_coreregister_u32(target_t *target,
                uint32_t *value, int regnum)
 {
@@ -311,12 +353,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
 {
        int retval = ERROR_OK;
        uint8_t Rd = regnum&0xFF;
+       uint32_t dscr;
 
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        armv7a_common_t *armv7a = armv4_5->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
-       
+
+       LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
+
+       /* Check that DCCRX is not full */
+       retval = mem_ap_read_atomic_u32(swjdp,
+                               armv7a->debug_base + CPUDBG_DSCR, &dscr);
+       if (dscr & (1 << DSCR_DTR_RX_FULL))
+       {
+               LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+               /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+       }
+
        if (Rd > 16)
                return retval;
 
@@ -610,9 +665,6 @@ int cortex_a8_debug_entry(target_t *target)
        cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-       if (armv7a->pre_debug_entry)
-               armv7a->pre_debug_entry(target);
-
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
        /* Enable the ITR execution once we are in debug mode */
@@ -1210,7 +1262,7 @@ int cortex_a8_assert_reset(target_t *target)
        armv4_5_invalidate_core_regs(target);
 
        target->state = TARGET_RESET;
-       
+
        return ERROR_OK;
 }
 
@@ -1305,6 +1357,8 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        exit(-1);
        }
 
+       if (target->state == TARGET_HALTED)
+       {
                /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
                /* invalidate I-Cache */
                if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
@@ -1322,6 +1376,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
                        for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
                                armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
                }
+       }
 
        return retval;
 }
@@ -1414,7 +1469,7 @@ int cortex_a8_examine(struct target_s *target)
        uint32_t didr, ctypr, ttypr, cpuid;
 
        LOG_DEBUG("TODO");
-       
+
        /* Here we shall insert a proper ROM Table scan */
        armv7a->debug_base = OMAP3530_DEBUG_BASE;
 
@@ -1491,7 +1546,7 @@ int cortex_a8_examine(struct target_s *target)
 
        /* Configure core debug access */
        cortex_a8_init_debug_access(target);
-       
+
        target->type->examined = 1;
 
        return retval;
@@ -1556,7 +1611,6 @@ LOG_DEBUG(" ");
        /* register arch-specific functions */
        armv7a->examine_debug_reason = NULL;
 
-       armv7a->pre_debug_entry = NULL;
        armv7a->post_debug_entry = cortex_a8_post_debug_entry;
 
        armv7a->pre_restore_context = NULL;