target/cortex_m: check core implementor field
[openocd.git] / src / target / cortex_m.c
index 987dc9b245164dd84c5934b7b42b4b868e43854e..87a88455270d836a4701ddf6f4840a3204fba16a 100644 (file)
 /* Supported Cortex-M Cores */
 static const struct cortex_m_part_info cortex_m_parts[] = {
        {
-               .partno = CORTEX_M0_PARTNO,
+               .impl_part = CORTEX_M0_PARTNO,
                .name = "Cortex-M0",
                .arch = ARM_ARCH_V6M,
        },
        {
-               .partno = CORTEX_M0P_PARTNO,
+               .impl_part = CORTEX_M0P_PARTNO,
                .name = "Cortex-M0+",
                .arch = ARM_ARCH_V6M,
        },
        {
-               .partno = CORTEX_M1_PARTNO,
+               .impl_part = CORTEX_M1_PARTNO,
                .name = "Cortex-M1",
                .arch = ARM_ARCH_V6M,
        },
        {
-               .partno = CORTEX_M3_PARTNO,
+               .impl_part = CORTEX_M3_PARTNO,
                .name = "Cortex-M3",
                .arch = ARM_ARCH_V7M,
                .flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
        },
        {
-               .partno = CORTEX_M4_PARTNO,
+               .impl_part = CORTEX_M4_PARTNO,
                .name = "Cortex-M4",
                .arch = ARM_ARCH_V7M,
                .flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
        },
        {
-               .partno = CORTEX_M7_PARTNO,
+               .impl_part = CORTEX_M7_PARTNO,
                .name = "Cortex-M7",
                .arch = ARM_ARCH_V7M,
                .flags = CORTEX_M_F_HAS_FPV5,
        },
        {
-               .partno = CORTEX_M23_PARTNO,
+               .impl_part = CORTEX_M23_PARTNO,
                .name = "Cortex-M23",
                .arch = ARM_ARCH_V8M,
        },
        {
-               .partno = CORTEX_M33_PARTNO,
+               .impl_part = CORTEX_M33_PARTNO,
                .name = "Cortex-M33",
                .arch = ARM_ARCH_V8M,
                .flags = CORTEX_M_F_HAS_FPV5,
        },
        {
-               .partno = CORTEX_M35P_PARTNO,
+               .impl_part = CORTEX_M35P_PARTNO,
                .name = "Cortex-M35P",
                .arch = ARM_ARCH_V8M,
                .flags = CORTEX_M_F_HAS_FPV5,
        },
        {
-               .partno = CORTEX_M55_PARTNO,
+               .impl_part = CORTEX_M55_PARTNO,
                .name = "Cortex-M55",
                .arch = ARM_ARCH_V8M,
                .flags = CORTEX_M_F_HAS_FPV5,
        },
        {
-               .partno = STAR_MC1_PARTNO,
+               .impl_part = STAR_MC1_PARTNO,
                .name = "STAR-MC1",
                .arch = ARM_ARCH_V8M,
                .flags = CORTEX_M_F_HAS_FPV5,
@@ -2526,18 +2526,18 @@ int cortex_m_examine(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               /* Get ARCH and CPU types */
-               const enum cortex_m_partno core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
+               /* Inspect implementor/part to look for recognized cores  */
+               unsigned int impl_part = cpuid & (ARM_CPUID_IMPLEMENTOR_MASK | ARM_CPUID_PARTNO_MASK);
 
                for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
-                       if (core_partno == cortex_m_parts[n].partno) {
+                       if (impl_part == cortex_m_parts[n].impl_part) {
                                cortex_m->core_info = &cortex_m_parts[n];
                                break;
                        }
                }
 
                if (!cortex_m->core_info) {
-                       LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is unrecognized", core_partno);
+                       LOG_TARGET_ERROR(target, "Cortex-M CPUID: 0x%x is unrecognized", cpuid);
                        return ERROR_FAIL;
                }
 
@@ -2549,7 +2549,7 @@ int cortex_m_examine(struct target *target)
                                (uint8_t)((cpuid >> 0) & 0xf));
 
                cortex_m->maskints_erratum = false;
-               if (core_partno == CORTEX_M7_PARTNO) {
+               if (impl_part == CORTEX_M7_PARTNO) {
                        uint8_t rev, patch;
                        rev = (cpuid >> 20) & 0xf;
                        patch = (cpuid >> 0) & 0xf;

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)