}
swjdp_transaction_endcheck(swjdp);
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
#ifdef ARMV7_GDB_HACKS
+ /* FIXME this breaks on scan chains with more than one Cortex-M3.
+ * Instead, each CM3 should have its own dummy value...
+ */
/* copy real xpsr reg for gdb, setting thumb bit */
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
target->state = TARGET_RESET;
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
while (timeout < 100)
{
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(armv7m->core_cache);
+
if (!debug_execution)
{
target->state = TARGET_RUNNING;
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
target->state = TARGET_RESET;
jtag_add_sleep(50000);
- armv7m_invalidate_core_regs(target);
+ register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (target->reset_halt)
{
if (CMD_ARGC > 0)
{
- if (!strcmp(CMD_ARGV[0], "on"))
- {
- cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
- }
- else if (!strcmp(CMD_ARGV[0], "off"))
- {
- cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
- }
- else
- {
- command_print(CMD_CTX, "usage: cortex_m3 maskisr ['on'|'off']");
- }
+ bool enable;
+ COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
+ uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0);
+ uint32_t mask_off = enable ? 0 : C_MASKINTS;
+ cortex_m3_write_debug_halt_mask(target, mask_on, mask_off);
}
command_print(CMD_CTX, "cortex_m3 interrupt mask %s",
return ERROR_OK;
}
-static int cortex_m3_register_commands(struct command_context *cmd_ctx)
-{
- int retval;
- struct command *cortex_m3_cmd;
-
- retval = armv7m_register_commands(cmd_ctx);
-
- cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
- NULL, COMMAND_ANY, "cortex_m3 specific commands");
-
- register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
- handle_cortex_m3_disassemble_command, COMMAND_EXEC,
- "disassemble Thumb2 instructions <address> [<count>]");
- register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
- handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
- "mask cortex_m3 interrupts ['on'|'off']");
- register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
- handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
- "catch hardware vectors ['all'|'none'|<list>]");
-
- return retval;
-}
+static const struct command_registration cortex_m3_exec_command_handlers[] = {
+ {
+ .name = "disassemble",
+ .handler = &handle_cortex_m3_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .help = "disassemble Thumb2 instructions",
+ .usage = "<address> [<count>]",
+ },
+ {
+ .name = "maskisr",
+ .handler = &handle_cortex_m3_mask_interrupts_command,
+ .mode = COMMAND_EXEC,
+ .help = "mask cortex_m3 interrupts",
+ .usage = "['on'|'off']",
+ },
+ {
+ .name = "vector_catch",
+ .handler = &handle_cortex_m3_vector_catch_command,
+ .mode = COMMAND_EXEC,
+ .help = "catch hardware vectors",
+ .usage = "['all'|'none'|<list>]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration cortex_m3_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = armv7m_command_handlers,
+ },
+ {
+ .name = "cortex_m3",
+ .mode = COMMAND_ANY,
+ .help = "Cortex-M3 command group",
+ .chain = cortex_m3_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
struct target_type cortexm3_target =
{
.add_watchpoint = cortex_m3_add_watchpoint,
.remove_watchpoint = cortex_m3_remove_watchpoint,
- .register_commands = cortex_m3_register_commands,
+ .commands = cortex_m3_command_handlers,
.target_create = cortex_m3_target_create,
.init_target = cortex_m3_init_target,
.examine = cortex_m3_examine,