extern reg_t armv7m_gdb_dummy_cpsr_reg;
#endif
-static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
uint32_t *value, int regnum)
{
int retval;
return retval;
}
-static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
uint32_t value, int regnum)
{
int retval;
static int cortex_m3_write_debug_halt_mask(target_t *target,
uint32_t mask_on, uint32_t mask_off)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
static int cortex_m3_clear_halt(target_t *target)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
static int cortex_m3_single_step_core(target_t *target)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dhcsr_save;
/* backup dhcsr reg */
{
int i;
uint32_t dcb_demcr;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
static int cortex_m3_examine_debug_reason(target_t *target)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
/* only check the debug reason if we don't know it already */
static int cortex_m3_examine_exception_reason(target_t *target)
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
switch (armv7m->exception_number)
int i;
uint32_t xPSR;
int retval;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
LOG_DEBUG(" ");
{
int retval;
enum target_state prev_target_state = target->state;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
static int cortex_m3_soft_reset_halt(struct target_s *target)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
static int cortex_m3_resume(struct target_s *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
breakpoint_t *breakpoint = NULL;
uint32_t resume_pc;
static int cortex_m3_step(struct target_s *target, int current,
uint32_t address, int handle_breakpoints)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
breakpoint_t *breakpoint = NULL;
if (target->state != TARGET_HALTED)
static int cortex_m3_assert_reset(target_t *target)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
int retval;
int fp_num = 0;
uint32_t hilo;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list;
if (breakpoint->set)
cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
if (!breakpoint->set)
static int
cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
if (cortex_m3->auto_bp_type)
{
static int
cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? FBP can be updated with core running ... */
if (target->state != TARGET_HALTED)
}
static int
-cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
uint32_t mask, temp;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* watchpoint params were validated earlier */
mask = 0;
}
static int
-cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
cortex_m3_dwt_comparator_t *comparator;
int dwt_num;
}
static int
-cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? DWT can be updated with core running ... */
if (target->state != TARGET_HALTED)
}
static int
-cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? DWT can be updated with core running ... */
if (target->state != TARGET_HALTED)
static void cortex_m3_enable_watchpoints(struct target_s *target)
{
- watchpoint_t *watchpoint = target->watchpoints;
+ struct watchpoint *watchpoint = target->watchpoints;
/* set any pending watchpoints */
while (watchpoint)
enum armv7m_regtype type, uint32_t num, uint32_t * value)
{
int retval;
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
{
int retval;
uint32_t reg;
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
}
static void
-cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target)
+cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
{
uint32_t dwtcr;
struct reg_cache_s *cache;
int retval;
uint32_t cpuid, fpcr;
int i;
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
static int cortex_m3_target_request_data(target_t *target,
uint32_t size, uint8_t *buffer)
{
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint8_t data;
uint8_t ctrl;
uint32_t i;
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
- struct armv7m_common_s *armv7m = target_to_armv7m(target);
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
}
static int cortex_m3_init_arch_info(target_t *target,
- cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
+ struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
{
int retval;
- struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
armv7m_init_arch_info(target, armv7m);
static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
{
- cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
+ struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
cortex_m3_init_arch_info(target, cortex_m3, target->tap);
/*--------------------------------------------------------------------------*/
static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx,
- struct cortex_m3_common_s *cm3)
+ struct cortex_m3_common *cm3)
{
if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
command_print(cmd_ctx, "target is not a Cortex-M3");
{
int retval;
target_t *target = get_current_target(cmd_ctx);
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
uint32_t address;
unsigned long count = 1;
arm_instruction_t cur_instruction;
COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
{
target_t *target = get_current_target(cmd_ctx);
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
- struct armv7m_common_s *armv7m = &cortex_m3->armv7m;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t demcr = 0;
int retval;
int i;
COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
{
target_t *target = get_current_target(cmd_ctx);
- struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
int retval;
retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);