Encapsulate the jtag_trst and jtag_srst variables:

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 68a23c0f72b67ff5605798b7d3c92cef72d6f18c..efa94ea4f1eb55e35604e7f149ef2c9568b01059 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -544,7 +544,7 @@ int cortex_m3_halt(target_t *target)
 
        if (target->state == TARGET_RESET)
        {
-               if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
+               if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_get_srst())
                {
                        LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
                        return ERROR_TARGET_FAILURE;
@@ -1564,9 +1564,12 @@ int cortex_m3_handle_target_request(void *priv)
 
 int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
 {
+       int retval;
        armv7m_common_t *armv7m;
        armv7m = &cortex_m3->armv7m;
 
+       armv7m_init_arch_info(target, armv7m);
+
        /* prepare JTAG information for the new target */
        cortex_m3->jtag_info.tap = tap;
        cortex_m3->jtag_info.scann_size = 4;
@@ -1575,6 +1578,8 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
        armv7m->swjdp_info.ap_csw_value = -1;
        armv7m->swjdp_info.ap_tar_value = -1;
        armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
+       armv7m->swjdp_info.memaccess_tck = 8;
+       armv7m->swjdp_info.tar_autoincr_block = (1<<12);        /* Cortex-M3 has 4096 bytes autoincrement range */
 
        /* initialize arch-specific breakpoint handling */
 
@@ -1590,13 +1595,17 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
        armv7m->pre_restore_context = NULL;
        armv7m->post_restore_context = NULL;
 
-       armv7m_init_arch_info(target, armv7m);
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
        armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
 
        target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
 
+       if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
+       {
+               return retval;
+       }
+
        return ERROR_OK;
 }