target/cortex_m: prevent asserting reset if examine is deferred

[openocd.git] / src / target / dsp563xx.c

diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 5ad52b58dcdad6f5f5a379ef166667d55d8d8f6a..80cca1ed5098d7110dcb7e0e8bf64376ec86f8cc 100644 (file)
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /***************************************************************************
  *   Copyright (C) 2009-2011 by Mathias Kuester                            *
  *   mkdorg@users.sourceforge.net                                          *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -96,10 +85,10 @@
 /*
  * OBCR Register bit definitions
  */
-#define OBCR_b0_and_b1            ((0x0) << 10)
-#define OBCR_b0_or_b1             ((0x1) << 10)
-#define OBCR_b1_after_b0          ((0x2) << 10)
-#define OBCR_b0_after_b1          ((0x3) << 10)
+#define OBCR_B0_AND_B1            ((0x0) << 10)
+#define OBCR_B0_OR_B1             ((0x1) << 10)
+#define OBCR_B1_AFTER_B0          ((0x2) << 10)
+#define OBCR_B0_AFTER_B1          ((0x3) << 10)
 
 #define OBCR_BP_DISABLED          (0x0)
 #define OBCR_BP_MEM_P             (0x1)
@@ -923,7 +912,7 @@ static int dsp563xx_examine(struct target *target)
 {
        uint32_t chip;
 
-       if (target->tap->hasidcode == false) {
+       if (!target->tap->has_idcode) {
                LOG_ERROR("no IDCODE present on device");
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
@@ -1307,7 +1296,7 @@ static int dsp563xx_step(struct target *target,
        struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -1385,14 +1374,14 @@ static int dsp563xx_run_algorithm(struct target *target,
        int num_mem_params, struct mem_param *mem_params,
        int num_reg_params, struct reg_param *reg_params,
        target_addr_t entry_point, target_addr_t exit_point,
-       int timeout_ms, void *arch_info)
+       unsigned int timeout_ms, void *arch_info)
 {
        int i;
        int retval = ERROR_OK;
        struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted (run target algo)");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -1716,7 +1705,7 @@ static int dsp563xx_write_memory_core(struct target *target,
                count);
 
        if (target->state != TARGET_HALTED) {
-               LOG_WARNING("target not halted");
+               LOG_TARGET_ERROR(target, "not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
@@ -1885,17 +1874,17 @@ static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *
        return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 }
 
-static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t memType,
+static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type,
                enum watchpoint_rw rw, enum watchpoint_condition cond)
 {
        int err = ERROR_OK;
        struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
 
-       bool wasRunning = false;
+       bool was_running = false;
        /* Only set breakpoint when halted */
        if (target->state != TARGET_HALTED) {
                dsp563xx_halt(target);
-               wasRunning = true;
+               was_running = true;
        }
 
        if (dsp563xx->hardware_breakpoint[0].used) {
@@ -1905,8 +1894,8 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
 
        uint32_t obcr_value = 0;
        if      (err == ERROR_OK) {
-               obcr_value |= OBCR_b0_or_b1;
-               switch (memType) {
+               obcr_value |= OBCR_B0_OR_B1;
+               switch (mem_type) {
                        case MEM_X:
                                obcr_value |= OBCR_BP_MEM_X;
                                break;
@@ -1917,7 +1906,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
                                obcr_value |= OBCR_BP_MEM_P;
                                break;
                        default:
-                               LOG_ERROR("Unknown memType parameter (%" PRIu32 ")", memType);
+                               LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type);
                                err = ERROR_TARGET_INVALID;
                }
        }
@@ -1981,7 +1970,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
        if (err == ERROR_OK)
                dsp563xx->hardware_breakpoint[0].used = BPU_WATCHPOINT;
 
-       if (err == ERROR_OK && wasRunning) {
+       if (err == ERROR_OK && was_running) {
                /* Resume from current PC */
                err = dsp563xx_resume(target, 1, 0x0, 0, 0);
        }
@@ -2151,7 +2140,7 @@ COMMAND_HANDLER(dsp563xx_mem_command)
                        COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count);
        }
 
-       buffer = calloc(count, sizeof(uint32_t));
+       buffer = calloc(count, 4);
 
        if (read_mem == 1) {
                err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),