#endif
#include "embeddedice.h"
+#include "register.h"
#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
static int embeddedice_reg_arch_type = -1;
-static int embeddedice_get_reg(reg_t *reg)
+static int embeddedice_get_reg(struct reg *reg)
{
int retval;
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
-reg_cache_t *
-embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
+struct reg_cache *
+embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
{
int retval;
- reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
- reg_t *reg_list = NULL;
- embeddedice_reg_t *arch_info = NULL;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
+ struct reg *reg_list = NULL;
+ struct embeddedice_reg *arch_info = NULL;
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
int i;
int eice_version = 0;
num_regs--;
/* the actual registers are kept in two arrays */
- reg_list = calloc(num_regs, sizeof(reg_t));
- arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
+ reg_list = calloc(num_regs, sizeof(struct reg));
+ arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
/* fill in values for the reg cache */
reg_cache->name = "EmbeddedICE registers";
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].arch_type = embeddedice_reg_arch_type;
/**
* Initialize EmbeddedICE module, if needed.
*/
-int embeddedice_setup(target_t *target)
+int embeddedice_setup(struct target *target)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* Explicitly disable monitor mode. For now we only support halting
* debug ... we don't know how to talk with a resident debug monitor
*/
if (arm7_9->has_monitor_mode)
{
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
* optionally checking the value read.
* Note that at this level, all registers are 32 bits wide.
*/
-int embeddedice_read_reg_w_check(reg_t *reg,
+int embeddedice_read_reg_w_check(struct reg *reg,
uint8_t *check_value, uint8_t *check_mask)
{
- embeddedice_reg_t *ice_reg = reg->arch_info;
+ struct embeddedice_reg *ice_reg = reg->arch_info;
uint8_t reg_addr = ice_reg->addr & 0x1f;
struct scan_field fields[3];
uint8_t field1_out[1];
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
-int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
+int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
{
struct scan_field fields[3];
uint8_t field1_out[1];
* Queue a read for an EmbeddedICE register into the register cache,
* not checking the value read.
*/
-int embeddedice_read_reg(reg_t *reg)
+int embeddedice_read_reg(struct reg *reg)
{
return embeddedice_read_reg_w_check(reg, NULL, NULL);
}
* Queue a write for an EmbeddedICE register, updating the register cache.
* Uses embeddedice_write_reg().
*/
-void embeddedice_set_reg(reg_t *reg, uint32_t value)
+void embeddedice_set_reg(struct reg *reg, uint32_t value)
{
embeddedice_write_reg(reg, value);
* Write an EmbeddedICE register, updating the register cache.
* Uses embeddedice_set_reg(); not queued.
*/
-int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
{
int retval;
/**
* Queue a write for an EmbeddedICE register, bypassing the register cache.
*/
-void embeddedice_write_reg(reg_t *reg, uint32_t value)
+void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
- embeddedice_reg_t *ice_reg = reg->arch_info;
+ struct embeddedice_reg *ice_reg = reg->arch_info;
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
* Queue a write for an EmbeddedICE register, using cached value.
* Uses embeddedice_write_reg().
*/
-void embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(struct reg *reg)
{
embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
* functional clock, so the 50+ JTAG clocks needed to receive the word
* allow hundreds of instruction cycles (per word) in the target.
*/
-int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size)
+int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
{
struct scan_field fields[3];
uint8_t field0_out[4];
/**
* Poll DCC control register until read or write handshake completes.
*/
-int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout)
+int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout)
{
struct scan_field fields[3];
uint8_t field0_in[4];