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breakpoint: -Wshadow warning fix
[openocd.git] / src / target / embeddedice.c
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index fe266d62814696324bc6c7e64402aab3dd7953c3..7ef4ac421b5aee57f69a245baaa6ca45ed63c6c7 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -47,6 +47,8 @@
  * core entered debug mode.
  */
 
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+
 /*
  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  */
@@ -343,10 +345,9 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        uint8_t field1_out[1];
        uint8_t field2_out[1];
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(ice_reg->jtag_info, 0x2);
+       arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
        /* bits 31:0 -- data (ignored here) */
        fields[0].num_bits = 32;
@@ -358,7 +359,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        /* bits 36:32 -- register */
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = reg_addr;
+       field1_out[0] = reg_addr;
        fields[1].in_value = NULL;
        fields[1].check_value = NULL;
        fields[1].check_mask = NULL;
@@ -366,7 +367,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        /* bit 37 -- 0/read */
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
        fields[2].check_value = NULL;
        fields[2].check_mask = NULL;
@@ -383,7 +384,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
         * EICE_COMMS_DATA would read the register twice
         * reading the control register is safe
         */
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
        /* traverse Update-DR, reading but with no other side effects */
        jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
@@ -405,9 +406,8 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
        uint8_t field1_out[1];
        uint8_t field2_out[1];
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -415,12 +415,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
 
        jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -431,7 +431,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
                 * to avoid reading additional data from the DCC data reg
                 */
                if (size == 1)
-                       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+                       field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
                fields[0].in_value = (uint8_t *)data;
                jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -471,7 +471,7 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
        int retval;
 
@@ -490,10 +490,9 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 
        LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(ice_reg->jtag_info, 0x2);
+       arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
        uint8_t reg_addr = ice_reg->addr & 0x1f;
        embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -523,9 +522,8 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
        uint8_t field1_out[1];
        uint8_t field2_out[1];
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
        fields[0].num_bits = 32;
        fields[0].out_value = field0_out;
@@ -533,18 +531,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 1;
+       field2_out[0] = 1;
 
        fields[2].in_value = NULL;
 
        while (size > 0)
        {
-               buf_set_u32(fields[0].out_value, 0, 32, *data);
+               buf_set_u32(field0_out, 0, 32, *data);
                jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
                data++;
@@ -576,9 +574,8 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
        else
                return ERROR_INVALID_ARGUMENTS;
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -586,12 +583,12 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
 
        jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
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