arm7_9->has_monitor_mode = 1;
break;
default:
+ /*
+ * The Feroceon implementation has the version number
+ * in some unusual bits. Let feroceon.c validate it
+ * and do the appropriate setup itself.
+ */
+ if (strcmp(target_get_name(target), "feroceon") == 0)
+ break;
LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
}
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
+ fields[0].check_value = NULL;
+ fields[0].check_mask = NULL;
fields[1].tap = ice_reg->jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].in_value = NULL;
+ fields[1].check_value = NULL;
+ fields[1].check_mask = NULL;
fields[2].tap = ice_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
+ fields[2].check_value = NULL;
+ fields[2].check_mask = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
fields[0].in_value = reg->value;
+ fields[0].check_value = check_value;
+ fields[0].check_mask = check_mask;
/* when reading the DCC data register, leaving the address field set to
* EICE_COMMS_DATA would read the register twice
*/
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
- jtag_add_dr_scan(3, fields, TAP_INVALID);
-
- jtag_check_value_mask(fields+0, check_value, check_mask);
+ jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
return ERROR_OK;
}
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
while (size > 0)
{
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
fields[0].in_value = (u8 *)data;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (u8 *)data);
data++;
LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
data++;
size--;
else
return ERROR_INVALID_ARGUMENTS;
- jtag_add_end_state(TAP_IDLE);
+ jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
gettimeofday(&lap, NULL);
do
{
- jtag_add_dr_scan(3, fields, TAP_INVALID);
+ jtag_add_dr_scan(3, fields, jtag_get_end_state());
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
return ERROR_TARGET_TIMEOUT;
}
+#ifndef HAVE_JTAG_MINIDRIVER_H
/* this is the inner loop of the open loop DCC write of data to target */
-void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
+void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count)
{
int i;
for (i = 0; i < count; i++)
buffer += 4;
}
}
+#else
+/* provided by minidriver */
+#endif