Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
- added mingw elf patches from Vincent Palatin
[openocd.git] / src / target / embeddedice.c
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 0cb4e01704b7af96674ca358fee1c727e105ef8a..ef38e13694a8a5f22a94be995aee664cf3dfa6ff 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -48,7 +48,8 @@ int embeddedice_reg_arch_info[] =
 {
        0x0, 0x1, 0x4, 0x5,
        0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
-       0x10, 0x11, 0x12, 0x13, 0x14, 0x15
+       0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+       0x2
 };
 
 char* embeddedice_reg_list[] =
@@ -71,29 +72,48 @@ char* embeddedice_reg_list[] =
        "watch 1 data value",
        "watch 1 data mask",
        "watch 1 control value",
-       "watch 1 control mask"
+       "watch 1 control mask",
+       
+       "vector catch"
 };
 
 int embeddedice_reg_arch_type = -1;
 
 int embeddedice_get_reg(reg_t *reg);
 int embeddedice_set_reg(reg_t *reg, u32 value);
+int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
 
 int embeddedice_write_reg(reg_t *reg, u32 value);
 int embeddedice_read_reg(reg_t *reg);
 
-reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg)
+int embeddedice_jtag_error_handler(u8 *in_value, void *priv)
+{
+       char *caller = priv;
+       
+       DEBUG("caller: %s", caller);
+       
+       return ERROR_OK;
+}
+
+reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
 {
        reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
        reg_t *reg_list = NULL;
        embeddedice_reg_t *arch_info = NULL;
-       int num_regs = 16 + extra_reg;
+       arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+       int num_regs;
        int i;
+       int eice_version = 0;
        
        /* register a register arch-type for EmbeddedICE registers only once */
        if (embeddedice_reg_arch_type == -1)
                embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
        
+       if (arm7_9->has_vector_catch)
+               num_regs = 17;
+       else
+               num_regs = 16;
+               
        /* the actual registers are kept in two arrays */
        reg_list = calloc(num_regs, sizeof(reg_t));
        arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
@@ -105,7 +125,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info
        reg_cache->num_regs = num_regs;
        
        /* set up registers */
-       for (i = 0; i < num_regs - extra_reg; i++)
+       for (i = 0; i < num_regs; i++)
        {
                reg_list[i].name = embeddedice_reg_list[i];
                reg_list[i].size = 32;
@@ -120,12 +140,63 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info
                arch_info[i].jtag_info = jtag_info;
        }
        
-       /* there may be one extra reg (Abort status (ARM7 rev4) or Vector catch (ARM9)) */
-       if (extra_reg)
+       /* identify EmbeddedICE version by reading DCC control register */
+       embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
+       jtag_execute_queue();
+       
+       eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
+       
+       switch (eice_version)
+       {
+               case 1:
+                       reg_list[EICE_DBG_CTRL].size = 3;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       break;
+               case 2:
+                       reg_list[EICE_DBG_CTRL].size = 4;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       arm7_9->has_single_step = 1;
+                       break;
+               case 3:
+                       ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); 
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       arm7_9->has_single_step = 1;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               case 4:
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               case 5:
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       arm7_9->has_single_step = 1;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               case 6:
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 10;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               case 7:
+                       WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
+                       reg_list[EICE_DBG_CTRL].size = 6;
+                       reg_list[EICE_DBG_STAT].size = 5;
+                       arm7_9->has_monitor_mode = 1;
+                       break;
+               default:
+                       ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+       }
+       
+       /* explicitly disable monitor mode */
+       if (arm7_9->has_monitor_mode)
        {
-               reg_list[num_regs - 1].arch_info = &arch_info[num_regs - 1];
-               reg_list[num_regs - 1].arch_type = embeddedice_reg_arch_type;
-               arch_info[num_regs - 1].jtag_info = jtag_info;
+               embeddedice_read_reg(&reg_list[EICE_DBG_CTRL]);
+               jtag_execute_queue();
+               buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
+               embeddedice_set_reg_w_exec(&reg_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value);
        }
        
        return reg_cache;
@@ -152,12 +223,17 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        embeddedice_reg_t *ice_reg = reg->arch_info;
        u8 reg_addr = ice_reg->addr & 0x1f;
        scan_field_t fields[3];
+       error_handler_t error_handler;
        
        DEBUG("%i", ice_reg->addr);
 
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(ice_reg->jtag_info, 0x2);
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
+       
+       error_handler.error_handler = embeddedice_jtag_error_handler;
+       error_handler.error_handler_priv = "embeddedice_read_reg_w_check";
+       
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, &error_handler);
        
        fields[0].device = ice_reg->jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -191,7 +267,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[2].in_handler = NULL;
        fields[2].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, -1, NULL);
        
        fields[0].in_value = reg->value;
        fields[0].in_check_value = check_value;
@@ -203,7 +279,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
         */
        buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
        
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, -1, NULL);
 
        free(fields[1].out_value);
        free(fields[2].out_value);
@@ -231,9 +307,9 @@ int embeddedice_set_reg(reg_t *reg, u32 value)
        return ERROR_OK;
 }
 
-int embeddedice_set_reg_w_exec(reg_t *reg, u32 value)
+int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 {
-       embeddedice_set_reg(reg, value);
+       embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
        
        if (jtag_execute_queue() != ERROR_OK)
        {
@@ -248,12 +324,17 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
        embeddedice_reg_t *ice_reg = reg->arch_info;
        u8 reg_addr = ice_reg->addr & 0x1f;
        scan_field_t fields[3];
+       error_handler_t error_handler;
        
        DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
        
        jtag_add_end_state(TAP_RTI);
        arm_jtag_scann(ice_reg->jtag_info, 0x2);
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr);
+       
+       error_handler.error_handler = embeddedice_jtag_error_handler;
+       error_handler.error_handler_priv = "embeddedice_write_reg";
+       
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
        
        fields[0].device = ice_reg->jtag_info->chain_pos;
        fields[0].num_bits = 32;
@@ -288,7 +369,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
        fields[2].in_handler = NULL;
        fields[2].in_handler_priv = NULL;
        
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, -1, NULL);
        
        free(fields[0].out_value);
        free(fields[1].out_value);
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)