cortex a8: fix segfault for unexamined targets
[openocd.git] / src / target / feroceon.c
index c912137627f6b32ce883c0b3ba8a04351adbab79..efd3040a9df4ce7e791abe8652c2c42ab59c024e 100644 (file)
@@ -84,29 +84,25 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 
        buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-       jtag_set_end_state(TAP_DRPAUSE);
-       arm_jtag_scann(jtag_info, 0x1);
+       arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
-       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = out_buf;
        fields[0].in_value = NULL;
 
-       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 3;
        fields[1].out_value = &sysspeed_buf;
        fields[1].in_value = NULL;
 
-       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 32;
        fields[2].out_value = instr_buf;
        fields[2].in_value = NULL;
 
-       jtag_add_dr_scan(3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
-       /* no jtag_add_runtest(0, jtag_get_end_state()) here */
+       /* no jtag_add_runtest(0, TAP_DRPAUSE) here */
 
        return ERROR_OK;
 }
@@ -337,7 +333,7 @@ void feroceon_branch_resume_thumb(struct target *target)
        struct arm7_9_common *arm7_9 = armv4_5->arch_info;
        struct arm_jtag *jtag_info = &arm7_9->jtag_info;
        uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-       uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
        arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -519,7 +515,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
        /* backup clobbered processor state */
        for (i = 0; i <= 5; i++)
                save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
-       save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       save[i] = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        /* set up target address in r0 */
        buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
@@ -572,9 +568,9 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
                armv4_5->core_cache->reg_list[i].valid = 1;
                armv4_5->core_cache->reg_list[i].dirty = 1;
        }
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
-       armv4_5->core_cache->reg_list[15].valid = 1;
-       armv4_5->core_cache->reg_list[15].dirty = 1;
+       buf_set_u32(armv4_5->pc->value, 0, 32, save[i]);
+       armv4_5->pc->valid = 1;
+       armv4_5->pc->dirty = 1;
        armv4_5->core_state = core_state;
 
        return retval;
@@ -694,7 +690,7 @@ struct target_type feroceon_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm926ejs_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,
        .write_memory = arm926ejs_write_memory,
@@ -721,7 +717,7 @@ struct target_type dragonite_target =
        .name = "dragonite",
 
        .poll = arm7_9_poll,
-       .arch_state = armv4_5_arch_state,
+       .arch_state = arm_arch_state,
 
        .target_request_data = arm7_9_target_request_data,
 
@@ -733,7 +729,7 @@ struct target_type dragonite_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm7_9_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm7_9_read_memory,
        .write_memory = arm7_9_write_memory,

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