#define MIPS32_CONFIG0_AR_SHIFT 10
#define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
+#define MIPS32_CONFIG1_FP_SHIFT 0
+#define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)
+
#define MIPS32_CONFIG1_DL_SHIFT 10
#define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
+#define MIPS32_CONFIG3_CDMM_SHIFT 3
+#define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)
+
+#define MIPS32_CONFIG3_DSPP_SHIFT 10
+#define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)
+
+#define MIPS32_CONFIG3_DSPREV_SHIFT 11
+#define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)
+
#define MIPS32_CONFIG3_ISA_SHIFT 14
#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
+#define MIPS32_NUM_DSPREGS 9
+
/* Bit Mask indicating CP0 register supported by this core */
#define MIPS_CP0_MK4 0x0001
#define MIPS_CP0_MAPTIV_UC 0x0002
/* CP1 FIR register fields */
#define MIPS32_CP1_FIR_F64_SHIFT 22
-static const struct {
+static const struct mips32_cp0 {
unsigned int reg;
unsigned int sel;
const char *name;
{31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
};
-#define MIPS32NUMCP0REGS ((int)ARRAY_SIZE(mips32_cp0_regs))
+#define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))
/* Insert extra NOPs after the DRET instruction on exit from debug. */
#define EJTAG_QUIRK_PAD_DRET BIT(0)
MIPS32_MMIPS32 = 3,
};
+/* Release 2~5 does not have much change regarding to the ISA under User mode,
+* therefore no new Architecture Revision(AR) level is assigned to them.
+* Release 6 changed some instruction's encoding/mnemonic, removed instructions that
+* has lost its purposes/none are using, and added some new instructions as well.
+*/
+enum mips32_isa_rel {
+ MIPS32_RELEASE_1 = 0,
+ MIPS32_RELEASE_2 = 1,
+ MIPS32_RELEASE_6 = 2,
+ MIPS32_RELEASE_UNKNOWN,
+};
+
+enum mips32_isa_supported {
+ MIPS16,
+ MIPS32,
+ MIPS64,
+ MICROMIPS_ONLY,
+ MIPS32_AT_RESET_AND_MICROMIPS,
+ MICROMIPS_AT_RESET_AND_MIPS32,
+};
+#define MIPS32_CORE_MASK 0xFFFFFF00
+#define MIPS32_VARIANT_MASK 0x00FF
+
+/* This struct contains mips cpu types with their name respectively.
+ * The PrID register format is as following:
+ * - Company Optionsp[31:24]
+ * - Company ID[23:16]
+ * - Processor ID[15:8]
+ * - Revision[7:0]
+ * Here the revision field represents the maximum value of revision.
+ */
+static const struct cpu_entry {
+ uint32_t prid;
+ enum mips32_isa_supported isa;
+ const char *vendor;
+ const char *cpu_name;
+} mips32_cpu_entry[] = {
+ /* MIPS Technologies cores */
+ {0x000180FF, MIPS32, "MIPS", "4Kc"},
+ {0x000181FF, MIPS64, "MIPS", "5Kc"},
+ {0x000182FF, MIPS64, "MIPS", "20Kc"},
+ {0x000183FF, MIPS32, "MIPS", "4KM"},
+
+ {0x000184FF, MIPS32, "MIPS", "4KEc"},
+ {0x000190FF, MIPS32, "MIPS", "4KEc"},
+
+ {0x000185FF, MIPS32, "MIPS", "4KEm"},
+ {0x000191FF, MIPS32, "MIPS", "4KEm"},
+
+ {0x000186FF, MIPS32, "MIPS", "4KSc"},
+ {0x000187FF, MIPS32, "MIPS", "M4K"},
+ {0x000188FF, MIPS64, "MIPS", "25Kf"},
+ {0x000189FF, MIPS64, "MIPS", "5KEc"},
+ {0x000192FF, MIPS32, "MIPS", "4KSD"},
+ {0x000193FF, MIPS32, "MIPS", "24Kc"},
+ {0x000195FF, MIPS32, "MIPS", "34Kc"},
+ {0x000196FF, MIPS32, "MIPS", "24KEc"},
+ {0x000197FF, MIPS32, "MIPS", "74Kc"},
+ {0x000199FF, MIPS32, "MIPS", "1004Kc"},
+ {0x00019AFF, MIPS32, "MIPS", "1074Kc"},
+ {0x00019BFF, MIPS32, "MIPS", "M14K"},
+ {0x00019CFF, MIPS32, "MIPS", "M14Kc"},
+ {0x00019DFF, MIPS32, "MIPS", "microAptiv_UC(M14KE)"},
+ {0x00019EFF, MIPS32, "MIPS", "microAptiv_UP(M14KEc)"},
+ {0x0001A0FF, MIPS32, "MIPS", "interAptiv"},
+ {0x0001A1FF, MIPS32, "MIPS", "interAptiv_CM"},
+ {0x0001A2FF, MIPS32, "MIPS", "proAptiv"},
+ {0x0001A3FF, MIPS32, "MIPS", "proAptiv_CM"},
+ {0x0001A6FF, MIPS32, "MIPS", "M5100"},
+ {0x0001A7FF, MIPS32, "MIPS", "M5150"},
+ {0x0001A8FF, MIPS32, "MIPS", "P5600"},
+ {0x0001A9FF, MIPS32, "MIPS", "I5500"},
+
+ /* Broadcom */
+ {0x000200FF, MIPS32, "Broadcom", "Broadcom"},
+
+ /* AMD Alchemy Series*/
+ /* NOTE: AMD/Alchemy series uses Company Option instead of
+ * Processor ID, to match the find function, Processor ID field
+ * is the copy of Company Option field */
+ {0x000300FF, MIPS32, "AMD Alchemy", "AU1000"},
+ {0x010301FF, MIPS32, "AMD Alchemy", "AU1500"},
+ {0x020302FF, MIPS32, "AMD Alchemy", "AU1100"},
+ {0x030303FF, MIPS32, "AMD Alchemy", "AU1550"},
+ {0x04030401, MIPS32, "AMD Alchemy", "AU1200"},
+ {0x040304FF, MIPS32, "AMD Alchemy", "AU1250"},
+ {0x050305FF, MIPS32, "AMD Alchemy", "AU1210"},
+
+ /* Altera */
+ {0x001000FF, MIPS32, "Altera", "Altera"},
+
+ /* Lexra */
+ {0x000B00FF, MIPS32, "Lexra", "Lexra"},
+
+ /* Ingenic */
+ {0x00e102FF, MIPS32, "Ingenic", "Ingenic XBurst rev1"},
+
+ {0xFFFFFFFF, MIPS32, "Unknown", "Unknown"}
+};
+
+#define MIPS32_NUM_CPU_ENTRIES (ARRAY_SIZE(mips32_cpu_entry))
+
+enum mips32_fp_imp {
+ MIPS32_FP_IMP_NONE = 0,
+ MIPS32_FP_IMP_32 = 1,
+ MIPS32_FP_IMP_64 = 2,
+ MIPS32_FP_IMP_UNKNOWN = 3,
+};
+
+enum mips32_dsp_imp {
+ MIPS32_DSP_IMP_NONE = 0,
+ MIPS32_DSP_IMP_REV1 = 1,
+ MIPS32_DSP_IMP_REV2 = 2,
+};
+
struct mips32_comparator {
int used;
uint32_t bp_value;
enum mips32_isa_mode isa_mode;
enum mips32_isa_imp isa_imp;
+ enum mips32_isa_rel isa_rel;
+ enum mips32_fp_imp fp_imp;
+ enum mips32_dsp_imp dsp_imp;
+
+ int fdc;
+ int semihosting;
+
+ /* The cp0 registers implemented on different processor cores could be different, too.
+ * Here you can see most of the registers are implemented on interAptiv, which is
+ * a 2c4t SMP processor, it has more features than M-class processors, like vpe
+ * and other config registers for multhreading. */
+ uint32_t cp0_mask;
+
+ /* FPU enabled (cp0.status.cu1) */
+ bool fpu_enabled;
+ /* FPU mode (cp0.status.fr) */
+ bool fpu_in_64bit;
/* processor identification register */
uint32_t prid;
+ /* detected CPU type */
+ const struct cpu_entry *cpu_info;
/* CPU specific quirks */
uint32_t cpu_quirks;
#define MIPS32_OP_XORI 0x0Eu
#define MIPS32_OP_XOR 0x26u
#define MIPS32_OP_SLTU 0x2Bu
-#define MIPS32_OP_SRL 0x03u
+#define MIPS32_OP_SRL 0x02u
+#define MIPS32_OP_SRA 0x03u
#define MIPS32_OP_SYNCI 0x1Fu
#define MIPS32_OP_SLL 0x00u
#define MIPS32_OP_SLTI 0x0Au
#define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
#define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
#define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
-#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
+#define MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA)
+#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL)
#define MIPS32_ISA_SYNC 0xFu
#define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
#define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
+/*
+ * MIPS32 Config1 Register (CP0 Register 16, Select 1)
+ */
+#define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */
+#define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */
+#define MIPS32_CFG1_MMUSSHIFT 25
+#define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */
+#define MIPS32_CFG1_ISSHIFT 22
+#define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */
+#define MIPS32_CFG1_ILSHIFT 19
+#define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */
+#define MIPS32_CFG1_IASHIFT 16
+#define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */
+#define MIPS32_CFG1_DSSHIFT 13
+#define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */
+#define MIPS32_CFG1_DLSHIFT 10
+#define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */
+#define MIPS32_CFG1_DASHIFT 7
+#define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */
+#define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */
+#define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */
+#define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */
+#define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */
+#define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */
+#define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */
+
+/*
+ * MIPS32 Coprocessor 0 register numbers
+ */
+#define MIPS32_C0_INDEX 0
+#define MIPS32_C0_INX 0
+#define MIPS32_C0_RANDOM 1
+#define MIPS32_C0_RAND 1
+#define MIPS32_C0_ENTRYLO0 2
+#define MIPS32_C0_TLBLO0 2
+#define MIPS32_C0_ENTRYLO1 3
+#define MIPS32_C0_TLBLO1 3
+#define MIPS32_C0_CONTEXT 4
+#define MIPS32_C0_CTXT 4
+#define MIPS32_C0_PAGEMASK 5
+#define MIPS32_C0_PAGEGRAIN (5, 1)
+#define MIPS32_C0_WIRED 6
+#define MIPS32_C0_HWRENA 7
+#define MIPS32_C0_BADVADDR 8
+#define MIPS32_C0_VADDR 8
+#define MIPS32_C0_COUNT 9
+#define MIPS32_C0_ENTRYHI 10
+#define MIPS32_C0_TLBHI 10
+#define MIPS32_C0_GUESTCTL1 10
+#define MIPS32_C0_COMPARE 11
+#define MIPS32_C0_STATUS 12
+#define MIPS32_C0_SR 12
+#define MIPS32_C0_INTCTL (12, 1)
+#define MIPS32_C0_SRSCTL (12, 2)
+#define MIPS32_C0_SRSMAP (12, 3)
+#define MIPS32_C0_CAUSE 13
+#define MIPS32_C0_CR 13
+#define MIPS32_C0_EPC 14
+#define MIPS32_C0_PRID 15
+#define MIPS32_C0_EBASE (15, 1)
+#define MIPS32_C0_CONFIG 16
+#define MIPS32_C0_CONFIG0 (16, 0)
+#define MIPS32_C0_CONFIG1 (16, 1)
+#define MIPS32_C0_CONFIG2 (16, 2)
+#define MIPS32_C0_CONFIG3 (16, 3)
+#define MIPS32_C0_LLADDR 17
+#define MIPS32_C0_WATCHLO 18
+#define MIPS32_C0_WATCHHI 19
+#define MIPS32_C0_DEBUG 23
+#define MIPS32_C0_DEPC 24
+#define MIPS32_C0_PERFCNT 25
+#define MIPS32_C0_ERRCTL 26
+#define MIPS32_C0_CACHEERR 27
+#define MIPS32_C0_TAGLO 28
+#define MIPS32_C0_ITAGLO 28
+#define MIPS32_C0_DTAGLO (28, 2)
+#define MIPS32_C0_TAGLO2 (28, 4)
+#define MIPS32_C0_DATALO (28, 1)
+#define MIPS32_C0_IDATALO (28, 1)
+#define MIPS32_C0_DDATALO (28, 3)
+#define MIPS32_C0_DATALO2 (28, 5)
+#define MIPS32_C0_TAGHI 29
+#define MIPS32_C0_ITAGHI 29
+#define MIPS32_C0_DATAHI (29, 1)
+#define MIPS32_C0_ERRPC 30
+#define MIPS32_C0_DESAVE 31
+
+/*
+ * MIPS32 MMU types
+ */
+#define MIPS32_MMU_TLB 1
+#define MIPS32_MMU_BAT 2
+#define MIPS32_MMU_FIXED 3
+#define MIPS32_MMU_DUAL_VTLB_FTLB 4
+
extern const struct command_registration mips32_command_handlers[];
int mips32_arch_state(struct target *target);
Code Review / openocd.git / blobdiff