target/xtensa: avoid IHI for writes to non-executable memory

[openocd.git] / src / target / mips32_pracc.h

diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index 587a446918d0f65eed425ccf96ebefc24e639807..f78f89153f65e1a7a5fd5b05b17bf897f77e405e 100644 (file)
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -53,6 +53,8 @@ struct pracc_queue_info {
        struct pa_list *pracc_list;     /* Code and store addresses at dmseg */
 };
 
+struct mips32_common;
+
 void pracc_queue_init(struct pracc_queue_info *ctx);
 void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
 void pracc_queue_free(struct pracc_queue_info *ctx);
@@ -101,6 +103,21 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info,
 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
                uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
 
+/**
+ * mips32_cp1_control_read
+ *
+ * @brief Simulates cfc1 ASM instruction (Move Control Word From Floating Point),
+ * i.e. implements copro C1 Control Register read.
+ *
+ * @param[in] ejtag_info
+ * @param[in] val Storage to hold read value
+ * @param[in] cp1_c_reg Number of copro C1 control register we want to read
+ *
+ * @return ERROR_OK on Success, ERROR_FAIL otherwise
+ */
+int mips32_cp1_control_read(struct mips_ejtag *ejtag_info,
+               uint32_t *val, uint32_t cp1_c_reg);
+
 static inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count)
 {
        if (ejtag_info->isa && ejtag_info->endianness)