target/cortex_m: Add Realtek Real-M200 and M300

[openocd.git] / src / target / mips64.c

diff --git a/src/target/mips64.c b/src/target/mips64.c
index f65aec114ee383d056da6444dea4021df5b0d4de..37f36855cb6416d2992423f95c9ebb2313be7c24 100644 (file)
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /*
  * Support for processors implementing MIPS64 instruction set
  *
@@ -10,16 +12,12 @@
  *   Copyright (C) 2008 by Spencer Oliver
  *   Copyright (C) 2008 by David T.L. Wong
  *   Copyright (C) 2010 by Konstantin Kostyukhin, Nikolay Shmyrev
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
  */
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
 
-#if BUILD_TARGET64 == 1
-
 #include "mips64.h"
 
 static const struct {
@@ -285,7 +283,7 @@ static int mips64_write_core_reg(struct target *target, int num)
 
        reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
        mips64->core_regs[num] = reg_value;
-       LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num , reg_value);
+       LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
        mips64->core_cache->reg_list[num].valid = 1;
        mips64->core_cache->reg_list[num].dirty = 0;
 
@@ -461,7 +459,7 @@ int mips64_init_arch_info(struct target *target, struct mips64_common *mips64,
 int mips64_run_algorithm(struct target *target, int num_mem_params,
                         struct mem_param *mem_params, int num_reg_params,
                         struct reg_param *reg_params, target_addr_t entry_point,
-                        target_addr_t exit_point, int timeout_ms, void *arch_info)
+                        target_addr_t exit_point, unsigned int timeout_ms, void *arch_info)
 {
        /* TODO */
        return ERROR_OK;
@@ -623,5 +621,3 @@ int mips64_enable_interrupts(struct target *target, bool enable)
 
        return ERROR_OK;
 }
-
-#endif /* BUILD_TARGET64 */