smp: replace commands smp_on/smp_off with "smp [on|off]"

[openocd.git] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 7d1c06cf06fb7e95c74012bda02e0ee0a96e3f04..016b5a9c52d9338849965380030c2895a8504f0c 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -33,6 +33,7 @@
 #include "mips32_dmaacc.h"
 #include "target_type.h"
 #include "register.h"
+#include "smp.h"
 
 static void mips_m4k_enable_breakpoints(struct target *target);
 static void mips_m4k_enable_watchpoints(struct target *target);
@@ -344,6 +345,8 @@ static int mips_m4k_assert_reset(struct target *target)
                        jtag_add_reset(1, 1);
                else if (!srst_asserted)
                        jtag_add_reset(0, 1);
+       } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+               target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
        } else {
                if (mips_m4k->is_pic32mx) {
                        LOG_DEBUG("Using MTAP reset to reset processor...");
@@ -456,8 +459,8 @@ static int mips_m4k_internal_restore(struct target *target, int current,
        if (!current) {
                mips_m4k_isa_filter(mips32->isa_imp, &address);
                buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
-               mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
-               mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+               mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+               mips32->core_cache->reg_list[MIPS32_PC].valid = true;
        }
 
        if ((mips32->isa_imp > 1) &&  debug_execution)  /* if more than one isa supported */
@@ -550,8 +553,8 @@ static int mips_m4k_step(struct target *target, int current,
        if (!current) {
                mips_m4k_isa_filter(mips32->isa_imp, &address);
                buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
-               mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
-               mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
+               mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
+               mips32->core_cache->reg_list[MIPS32_PC].valid = true;
        }
 
        /* the front-end may request us not to handle breakpoints */
@@ -702,7 +705,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
                        }
 
                        if (verify == 0) {
-                               LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
+                               LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
                                        " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
@@ -723,7 +726,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
                                return retval;
 
                        if (verify != MIPS16_SDBBP(isa_req)) {
-                               LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
+                               LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
                                                " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
@@ -1331,43 +1334,6 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
        return ERROR_OK;
 }
 
-COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
-{
-       struct target *target = get_current_target(CMD_CTX);
-       /* check target is an smp target */
-       struct target_list *head;
-       struct target *curr;
-       head = target->head;
-       target->smp = 0;
-       if (head != (struct target_list *)NULL) {
-               while (head != (struct target_list *)NULL) {
-                       curr = head->target;
-                       curr->smp = 0;
-                       head = head->next;
-               }
-               /*  fixes the target display to the debugger */
-               target->gdb_service->target = target;
-       }
-       return ERROR_OK;
-}
-
-COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
-{
-       struct target *target = get_current_target(CMD_CTX);
-       struct target_list *head;
-       struct target *curr;
-       head = target->head;
-       if (head != (struct target_list *)NULL) {
-               target->smp = 1;
-               while (head != (struct target_list *)NULL) {
-                       curr = head->target;
-                       curr->smp = 1;
-                       head = head->next;
-               }
-       }
-       return ERROR_OK;
-}
-
 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
 {
        struct target *target = get_current_target(CMD_CTX);
@@ -1420,20 +1386,6 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = {
                .usage = "regnum [value]",
                .help = "display/modify cp0 register",
        },
-       {
-               .name = "smp_off",
-               .handler = mips_m4k_handle_smp_off_command,
-               .mode = COMMAND_EXEC,
-               .help = "Stop smp handling",
-               .usage = "",},
-
-       {
-               .name = "smp_on",
-               .handler = mips_m4k_handle_smp_on_command,
-               .mode = COMMAND_EXEC,
-               .help = "Restart smp handling",
-               .usage = "",
-       },
        {
                .name = "smp_gdb",
                .handler = mips_m4k_handle_smp_gdb_command,
@@ -1448,6 +1400,9 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = {
                .help = "display/set scan delay in nano seconds",
                .usage = "[value]",
        },
+       {
+               .chain = smp_command_handlers,
+       },
        COMMAND_REGISTRATION_DONE
 };