cortex a8: fix segfault for unexamined targets

[openocd.git] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index f581ddf152d50aef906c57a439d141d5e95eb72a..e258b714e44dfbd0b4ac9db5d26867a09d941e76 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -112,8 +112,7 @@ int mips_m4k_poll(struct target *target)
        uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 
        /* read ejtag control reg */
-       jtag_set_end_state(TAP_IDLE);
-       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
        mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        /* clear this bit before handling polling
@@ -122,10 +121,9 @@ int mips_m4k_poll(struct target *target)
        {
                /* we have detected a reset, clear flag
                 * otherwise ejtag will not work */
-               jtag_set_end_state(TAP_IDLE);
                ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
                mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
                LOG_DEBUG("Reset Detected");
        }
@@ -135,8 +133,7 @@ int mips_m4k_poll(struct target *target)
        {
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
-                       jtag_set_end_state(TAP_IDLE);
-                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 
                        target->state = TARGET_HALTED;
 
@@ -212,39 +209,29 @@ int mips_m4k_halt(struct target *target)
 
 int mips_m4k_assert_reset(struct target *target)
 {
-       struct mips32_common *mips32 = target_to_mips32(target);
-       struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+       struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+       struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+       int assert_srst = 1;
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
+
        if (!(jtag_reset_config & RESET_HAS_SRST))
-       {
-               LOG_ERROR("Can't assert SRST");
-               return ERROR_FAIL;
-       }
+               assert_srst = 0;
 
        if (target->reset_halt)
        {
                /* use hardware to catch reset */
-               jtag_set_end_state(TAP_IDLE);
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
+               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
        }
        else
        {
-               jtag_set_end_state(TAP_IDLE);
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
        }
 
-       if (strcmp(target->variant, "ejtag_srst") == 0)
-       {
-               uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
-               LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       }
-       else
+       if (assert_srst)
        {
                /* here we should issue a srst only, but we may have to assert trst as well */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -256,11 +243,38 @@ int mips_m4k_assert_reset(struct target *target)
                        jtag_add_reset(0, 1);
                }
        }
+       else
+       {
+               if (mips_m4k->is_pic32mx)
+               {
+                       uint32_t mchip_cmd;
+
+                       LOG_DEBUG("Using MTAP reset to reset processor...");
+
+                       /* use microchip specific MTAP reset */
+                       mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+                       mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
+
+                       mchip_cmd = MCHP_ASERT_RST;
+                       mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+                       mchip_cmd = MCHP_DE_ASSERT_RST;
+                       mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+                       mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
+               }
+               else
+               {
+                       /* use ejtag reset - not supported by all cores */
+                       uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+                       LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
+                       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+               }
+       }
 
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 
-       register_cache_invalidate(mips32->core_cache);
+       register_cache_invalidate(mips_m4k->mips32.core_cache);
 
        if (target->reset_halt)
        {
@@ -878,7 +892,7 @@ int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
 int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
                struct jtag_tap *tap)
 {
-       struct mips32_common *mips32 = &mips_m4k->mips32_common;
+       struct mips32_common *mips32 = &mips_m4k->mips32;
 
        mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 
@@ -901,8 +915,8 @@ int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 int mips_m4k_examine(struct target *target)
 {
        int retval;
-       struct mips32_common *mips32 = target_to_mips32(target);
-       struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+       struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+       struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
        uint32_t idcode = 0;
 
        if (!target_was_examined(target))
@@ -914,8 +928,9 @@ int mips_m4k_examine(struct target *target)
                {
                        /* we are using a pic32mx so select ejtag port
                         * as it is not selected by default */
-                       mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
+                       mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
                        LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+                       mips_m4k->is_pic32mx = true;
                }
        }
 
@@ -936,7 +951,7 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
        struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
        struct working_area *source;
        int retval;
-       int write = 1;
+       int write_t = 1;
 
        LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
 
@@ -969,7 +984,7 @@ int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
                }
        }
 
-       retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address,
+       retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write_t, address,
                        count, (uint32_t*) buffer);
        if (retval != ERROR_OK)
        {