return ERROR_OK;
}
-int xscale_jtag_callback(enum jtag_event event, void *priv)
-{
- switch (event)
- {
- case JTAG_TRST_ASSERTED:
- break;
- case JTAG_TRST_RELEASED:
- break;
- case JTAG_SRST_ASSERTED:
- break;
- case JTAG_SRST_RELEASED:
- break;
- default:
- WARNING("unhandled JTAG event");
- }
-
- return ERROR_OK;
-}
-
int xscale_read_dcsr(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
- /* fields[0].in_value = field0; */
+ fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
fields[1].device = xscale->jtag_info.chain_pos;
jtag_add_end_state(TAP_RTI);
xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
- jtag_add_runtest(1, -1);
+ jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts=0;
if (attempts++==1000)
{
ERROR("Failed to receiving data from debug handler after 1000 attempts");
- retval=ERROR_JTAG_QUEUE_FAILED;
+ retval=ERROR_TARGET_TIMEOUT;
break;
}
}
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
enum tap_state path[3];
- enum tap_state noconsume_path[9];
+ enum tap_state noconsume_path[6];
int retval;
struct timeval timeout, now;
noconsume_path[2] = TAP_E1D;
noconsume_path[3] = TAP_PD;
noconsume_path[4] = TAP_E2D;
- noconsume_path[5] = TAP_UD;
- noconsume_path[6] = TAP_SDS;
- noconsume_path[7] = TAP_CD;
- noconsume_path[8] = TAP_SD;
+ noconsume_path[5] = TAP_SD;
fields[0].device = xscale->jtag_info.chain_pos;
fields[0].num_bits = 3;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
gettimeofday(&timeout, NULL);
- timeval_add_time(&timeout, 5, 0);
+ timeval_add_time(&timeout, 1, 0);
- do
+ for (;;)
{
- /* if we want to consume the register content (i.e. clear TX_READY),
- * we have to go straight from Capture-DR to Shift-DR
- * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
- */
- if (consume)
- jtag_add_pathmove(3, path);
- else
- jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
-
- jtag_add_dr_scan(3, fields, TAP_RTI);
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- ERROR("JTAG error while reading TX");
- return ERROR_TARGET_TIMEOUT;
- }
-
- gettimeofday(&now, NULL);
- if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
+ int i;
+ for (i=0; i<100; i++)
{
- ERROR("time out reading TX register");
- return ERROR_TARGET_TIMEOUT;
+ /* if we want to consume the register content (i.e. clear TX_READY),
+ * we have to go straight from Capture-DR to Shift-DR
+ * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
+ */
+ if (consume)
+ jtag_add_pathmove(3, path);
+ else
+ {
+ jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
+ }
+
+ jtag_add_dr_scan(3, fields, TAP_RTI);
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ ERROR("JTAG error while reading TX");
+ return ERROR_TARGET_TIMEOUT;
+ }
+
+ gettimeofday(&now, NULL);
+ if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
+ {
+ ERROR("time out reading TX register");
+ return ERROR_TARGET_TIMEOUT;
+ }
+ if (!((!(field0_in & 1)) && consume))
+ {
+ goto done;
+ }
}
- } while ((!(field0_in & 1)) && consume);
+ DEBUG("waiting 10ms");
+ usleep(10*1000); /* avoid flooding the logs */
+ }
+ done:
if (!(field0_in & 1))
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
gettimeofday(&timeout, NULL);
- timeval_add_time(&timeout, 5, 0);
+ timeval_add_time(&timeout, 1, 0);
/* poll until rx_read is low */
DEBUG("polling RX");
- do
+ for (;;)
{
- jtag_add_dr_scan(3, fields, TAP_RTI);
-
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- ERROR("JTAG error while writing RX");
- return retval;
- }
-
- gettimeofday(&now, NULL);
- if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
+ int i;
+ for (i=0; i<10; i++)
{
- ERROR("time out writing RX register");
- return ERROR_TARGET_TIMEOUT;
+ jtag_add_dr_scan(3, fields, TAP_RTI);
+
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ ERROR("JTAG error while writing RX");
+ return retval;
+ }
+
+ gettimeofday(&now, NULL);
+ if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
+ {
+ ERROR("time out writing RX register");
+ return ERROR_TARGET_TIMEOUT;
+ }
+ if (!(field0_in & 1))
+ goto done;
}
- } while (field0_in & 1);
-
+ DEBUG("waiting 10ms");
+ usleep(10*1000); /* wait 10ms to avoid flooding the logs */
+ }
+ done:
+
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(3, fields, TAP_RTI);
fields[0].out_value = &field0_out;
fields[0].out_mask = NULL;
fields[0].in_handler = NULL;
+ fields[0].in_value = NULL;
if (!xscale->fast_memory_access)
{
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
int i;
+ int retval;
u32 low_reset_branch, high_reset_branch;
}
else
{
- if (target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]) != ERROR_OK)
+ retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
+ if (retval == ERROR_TARGET_TIMEOUT)
+ return retval;
+ if (retval!=ERROR_OK)
{
+ /* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
else
{
- if (target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]) != ERROR_OK)
+ retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
+ if (retval == ERROR_TARGET_TIMEOUT)
+ return retval;
+ if (retval!=ERROR_OK)
{
+ /* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
u32 pc;
u32 buffer[10];
int i;
+ int retval;
u32 moe;
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
- xscale_read_dcsr(target);
-
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
+
/* get r0, pc, r1 to r7 and cpsr */
- xscale_receive(target, buffer, 10);
+ if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
+ return retval;
/* move r0 from buffer to register cache */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ return ERROR_OK;
}
else if (target->state == TARGET_UNKNOWN)
{
}
/* update vector tables */
- xscale_update_vectors(target);
+ if ((retval=xscale_update_vectors(target))!=ERROR_OK)
+ return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
DEBUG("target->state: %s", target_state_strings[target->state]);
+ /* TRST every time. We want to be able to support daemon_startup attach */
+ jtag_add_reset(1, 0);
+ jtag_add_sleep(5000);
+ jtag_add_reset(0, 0);
+ jtag_add_sleep(5000);
+ jtag_execute_queue();
+
+
+
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
xscale_common_t *xscale = armv4_5->arch_info;
u32 *buf32;
int i;
+ int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
- xscale_send_u32(target, 0x10 | size);
+ if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
+ return retval;
/* send base address for read request */
- xscale_send_u32(target, address);
+ if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ return retval;
/* send number of requested data words */
- xscale_send_u32(target, count);
+ if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
- xscale_receive(target, buf32, count);
+ if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
+ return retval;
/* extract data from host-endian buffer into byte stream */
for (i = 0; i < count; i++)
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
- xscale_read_dcsr(target);
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- xscale_send_u32(target, 0x60);
+ if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ return retval;
return ERROR_TARGET_DATA_ABORT;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
+ int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
- xscale_send_u32(target, 0x20 | size);
+ if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
+ return retval;
/* send base address for read request */
- xscale_send_u32(target, address);
+ if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ return retval;
/* send number of requested data words to be written*/
- xscale_send_u32(target, count);
+ if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ return retval;
/* extract data from host-endian buffer into byte stream */
#if 0
}
}
#endif
- xscale_send(target, buffer, count, size);
+ if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
+ return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
- xscale_read_dcsr(target);
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- xscale_send_u32(target, 0x60);
+ if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ return retval;
return ERROR_TARGET_DATA_ABORT;
}
int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
- if (startup_mode != DAEMON_RESET)
- {
- ERROR("XScale target requires a reset");
- ERROR("Reset target to enable debug");
- }
-
- /* assert TRST once during startup */
- jtag_add_reset(1, 0);
- jtag_add_sleep(5000);
- jtag_add_reset(0, 0);
- jtag_execute_queue();
-
return ERROR_OK;
}
/* prepare JTAG information for the new target */
xscale->jtag_info.chain_pos = chain_pos;
- jtag_register_event_callback(xscale_jtag_callback, target);
xscale->jtag_info.dbgrx = 0x02;
xscale->jtag_info.dbgtx = 0x10;
int chain_pos;
char *variant = NULL;
xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
+ memset(xscale, 0, sizeof(*xscale));
if (argc < 5)
{
Code Review / openocd.git / blobdiff