target/adi_v5_swd: add support for SWD multidrop

[openocd.git] / src / target / xscale.c

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 1bca96d73e9004d060225a61cbe711dd38458c6f..dd383b6e46d50ef831ab23562d637ca09df9411e 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -150,7 +150,7 @@ static int xscale_verify_pointer(struct command_invocation *cmd,
 
 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 {
-       assert(tap != NULL);
+       assert(tap);
 
        if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
                struct scan_field field;
@@ -824,7 +824,7 @@ static int xscale_poll(struct target *target)
                        retval = xscale_debug_entry(target);
                } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
                        LOG_USER("error while polling TX register, reset CPU");
-                       /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
+                       /* here we "lie" so GDB won't get stuck and a reset can be performed */
                        target->state = TARGET_HALTED;
                }
 
@@ -955,7 +955,7 @@ static int xscale_debug_entry(struct target *target)
                        xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
                        pc -= 4;
                        break;
-               case 0x5:       /* Vector trap occured */
+               case 0x5:       /* Vector trap occurred */
                        target->debug_reason = DBG_REASON_BREAKPOINT;
                        xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
                        pc -= 4;
@@ -1110,8 +1110,7 @@ static void xscale_free_trace_data(struct xscale_common *xscale)
        struct xscale_trace_data *td = xscale->trace.data;
        while (td) {
                struct xscale_trace_data *next_td = td->next;
-               if (td->entries)
-                       free(td->entries);
+               free(td->entries);
                free(td);
                td = next_td;
        }
@@ -1159,7 +1158,7 @@ static int xscale_resume(struct target *target, int current,
                struct breakpoint *breakpoint;
                breakpoint = breakpoint_find(target,
                                buf_get_u32(arm->pc->value, 0, 32));
-               if (breakpoint != NULL) {
+               if (breakpoint) {
                        uint32_t next_pc;
                        enum trace_mode saved_trace_mode;
 
@@ -1422,7 +1421,7 @@ static int xscale_step(struct target *target, int current,
        if (handle_breakpoints)
                breakpoint = breakpoint_find(target,
                                buf_get_u32(arm->pc->value, 0, 32));
-       if (breakpoint != NULL) {
+       if (breakpoint) {
                retval = xscale_unset_breakpoint(target, breakpoint);
                if (retval != ERROR_OK)
                        return retval;
@@ -2412,7 +2411,7 @@ static int xscale_get_reg(struct reg *reg)
        } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
                /* can't (explicitly) read from TXRXCTRL register */
                return ERROR_OK;
-       } else {/* Other DBG registers have to be transfered by the debug handler
+       } else {/* Other DBG registers have to be transferred by the debug handler
                 * send CP read request (command 0x40) */
                xscale_send_u32(target, 0x40);
 
@@ -2450,7 +2449,7 @@ static int xscale_set_reg(struct reg *reg, uint8_t *buf)
        } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
                /* can't (explicitly) write to TXRXCTRL register */
                return ERROR_OK;
-       } else {/* Other DBG registers have to be transfered by the debug handler
+       } else {/* Other DBG registers have to be transferred by the debug handler
                 * send CP write request (command 0x41) */
                xscale_send_u32(target, 0x41);
 
@@ -2583,7 +2582,6 @@ static int xscale_read_instruction(struct target *target, uint32_t pc,
        struct arm_instruction *instruction)
 {
        struct xscale_common *const xscale = target_to_xscale(target);
-       int i;
        int section = -1;
        size_t size_read;
        uint32_t opcode;
@@ -2593,7 +2591,7 @@ static int xscale_read_instruction(struct target *target, uint32_t pc,
                return ERROR_TRACE_IMAGE_UNAVAILABLE;
 
        /* search for the section the current instruction belongs to */
-       for (i = 0; i < xscale->trace.image->num_sections; i++) {
+       for (unsigned int i = 0; i < xscale->trace.image->num_sections; i++) {
                if ((xscale->trace.image->sections[i].base_address <= pc) &&
                        (xscale->trace.image->sections[i].base_address +
                        xscale->trace.image->sections[i].size > pc)) {
@@ -2809,7 +2807,7 @@ static int xscale_analyze_trace(struct target *target, struct command_invocation
                                                current_pc = chkpt_reg;
                                        else if (current_pc != chkpt_reg)       /* sanity check */
                                                LOG_WARNING("trace is suspect: checkpoint register "
-                                                       "inconsistent with adddress from image");
+                                                       "inconsistent with address from image");
                                }
 
                                if (current_pc == 0)
@@ -2884,7 +2882,7 @@ static void xscale_build_reg_cache(struct target *target)
        /* fill in values for the xscale reg cache */
        (*cache_p)->name = "XScale registers";
        (*cache_p)->next = NULL;
-       (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
+       (*cache_p)->reg_list = calloc(num_regs, sizeof(struct reg));
        (*cache_p)->num_regs = num_regs;
 
        for (i = 0; i < num_regs; i++) {
@@ -2942,7 +2940,7 @@ static int xscale_init_arch_info(struct target *target,
 
        arm = &xscale->arm;
 
-       /* store architecture specfic data */
+       /* store architecture specific data */
        xscale->common_magic = XSCALE_COMMON_MAGIC;
 
        /* PXA3xx with 11 bit IR shifts the JTAG instructions */
@@ -3050,7 +3048,7 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
        target = get_target(CMD_ARGV[0]);
-       if (target == NULL) {
+       if (!target) {
                LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
                return ERROR_FAIL;
        }
@@ -3085,7 +3083,7 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
        target = get_target(CMD_ARGV[0]);
-       if (target == NULL) {
+       if (!target) {
                LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
                return ERROR_FAIL;
        }
@@ -3429,15 +3427,15 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
        }
 
        xscale->trace.image = malloc(sizeof(struct image));
-       xscale->trace.image->base_address_set = 0;
-       xscale->trace.image->start_address_set = 0;
+       xscale->trace.image->base_address_set = false;
+       xscale->trace.image->start_address_set = false;
 
        /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
        if (CMD_ARGC >= 2) {
-               xscale->trace.image->base_address_set = 1;
+               xscale->trace.image->base_address_set = true;
                COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
        } else
-               xscale->trace.image->base_address_set = 0;
+               xscale->trace.image->base_address_set = false;
 
        if (image_open(xscale->trace.image, CMD_ARGV[0],
                (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {