Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag: retire one instance of jtag_get_end_state() usage
[openocd.git] / src / target / xscale.c
diff --git a/src/target/xscale.c b/src/target/xscale.c
index fc71ea3347018a0ff2796cdede60bfcd6d62f7b0..f5aada507d54557826091ab95ff865f4ef228b33 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -169,12 +169,11 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
                uint8_t scratch[4];
 
                memset(&field, 0, sizeof field);
-               field.tap = tap;
                field.num_bits = tap->ir_length;
                field.out_value = scratch;
                buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 
-               jtag_add_ir_scan(1, &field, jtag_get_end_state());
+               jtag_add_ir_scan(tap, &field, jtag_get_end_state());
        }
 
        return ERROR_OK;
@@ -201,23 +200,20 @@ static int xscale_read_dcsr(struct target *target)
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 3;
        fields[0].out_value = &field0;
        uint8_t tmp;
        fields[0].in_value = &tmp;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 32;
        fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 
-       fields[2].tap = target->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = &field2;
        uint8_t tmp2;
        fields[2].in_value = &tmp2;
 
-       jtag_add_dr_scan(3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 
        jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
        jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -240,7 +236,7 @@ static int xscale_read_dcsr(struct target *target)
 
        jtag_set_end_state(TAP_IDLE);
 
-       jtag_add_dr_scan(3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 
        /* DANGER!!! this must be here. It will make sure that the arguments
         * to jtag_set_check_value() does not go out of scope! */
@@ -279,15 +275,12 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 3;
        fields[0].check_value = &field0_check_value;
        fields[0].check_mask = &field0_check_mask;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 32;
 
-       fields[2].tap = target->tap;
        fields[2].num_bits = 1;
        fields[2].check_value = &field2_check_value;
        fields[2].check_mask = &field2_check_mask;
@@ -295,7 +288,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
        jtag_set_end_state(TAP_IDLE);
        xscale_jtag_set_instr(target->tap,
                XSCALE_DBGTX << xscale->xscale_variant);
-       jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
+       jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 
        /* repeat until all words have been collected */
        int attempts = 0;
@@ -311,7 +304,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
 
                        fields[1].in_value = (uint8_t *)(field1 + i);
 
-                       jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
+                       jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
 
                        jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
 
@@ -392,15 +385,12 @@ static int xscale_read_tx(struct target *target, int consume)
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 3;
        fields[0].in_value = &field0_in;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 32;
        fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 
-       fields[2].tap = target->tap;
        fields[2].num_bits = 1;
        uint8_t tmp;
        fields[2].in_value = &tmp;
@@ -421,7 +411,7 @@ static int xscale_read_tx(struct target *target, int consume)
                        jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
                }
 
-               jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+               jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 
                jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
                jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -480,16 +470,13 @@ static int xscale_write_rx(struct target *target)
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 3;
        fields[0].out_value = &field0_out;
        fields[0].in_value = &field0_in;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 32;
        fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 
-       fields[2].tap = target->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = &field2;
        uint8_t tmp;
@@ -502,7 +489,7 @@ static int xscale_write_rx(struct target *target)
        LOG_DEBUG("polling RX");
        for (;;)
        {
-               jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+               jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 
                jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
                jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -534,7 +521,7 @@ static int xscale_write_rx(struct target *target)
 
        /* set rx_valid */
        field2 = 0x1;
-       jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
+       jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
@@ -598,7 +585,7 @@ static int xscale_send(struct target *target, uint8_t *buffer, int count, int si
                                3,
                                bits,
                                t,
-                               jtag_set_end_state(TAP_IDLE));
+                               TAP_IDLE);
                buffer += size;
        }
 
@@ -646,23 +633,20 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 3;
        fields[0].out_value = &field0;
        uint8_t tmp;
        fields[0].in_value = &tmp;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 32;
        fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 
-       fields[2].tap = target->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = &field2;
        uint8_t tmp2;
        fields[2].in_value = &tmp2;
 
-       jtag_add_dr_scan(3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 
        jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
        jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -717,15 +701,13 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 6;
        fields[0].out_value = &cmd;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 27;
        fields[1].out_value = packet;
 
-       jtag_add_dr_scan(2, fields, jtag_get_end_state());
+       jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 
        /* rest of packet is a cacheline: 8 instructions, with parity */
        fields[0].num_bits = 32;
@@ -742,7 +724,7 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
                memcpy(&value, packet, sizeof(uint32_t));
                cmd = parity(value);
 
-               jtag_add_dr_scan(2, fields, jtag_get_end_state());
+               jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
        }
 
        return jtag_execute_queue();
@@ -767,15 +749,13 @@ static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 
        memset(&fields, 0, sizeof fields);
 
-       fields[0].tap = target->tap;
        fields[0].num_bits = 6;
        fields[0].out_value = &cmd;
 
-       fields[1].tap = target->tap;
        fields[1].num_bits = 27;
        fields[1].out_value = packet;
 
-       jtag_add_dr_scan(2, fields, jtag_get_end_state());
+       jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 
        return ERROR_OK;
 }
@@ -941,9 +921,9 @@ static int xscale_debug_entry(struct target *target)
        LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 
        /* move pc from buffer to register cache */
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
-       armv4_5->core_cache->reg_list[15].dirty = 1;
-       armv4_5->core_cache->reg_list[15].valid = 1;
+       buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]);
+       armv4_5->pc->dirty = 1;
+       armv4_5->pc->valid = 1;
        LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 
        /* move data from buffer to register cache */
@@ -995,7 +975,7 @@ static int xscale_debug_entry(struct target *target)
        moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
 
        /* stored PC (for calculating fixup) */
-       pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        switch (moe)
        {
@@ -1042,7 +1022,7 @@ static int xscale_debug_entry(struct target *target)
        }
 
        /* apply PC fixup */
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
+       buf_set_u32(armv4_5->pc->value, 0, 32, pc);
 
        /* on the first debug entry, identify cache type */
        if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
@@ -1212,21 +1192,23 @@ static int xscale_resume(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
-               buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+               buf_set_u32(armv4_5->pc->value, 0, 32, address);
 
-       current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        /* if we're at the reset vector, we have to simulate the branch */
        if (current_pc == 0x0)
        {
                arm_simulate_step(target, NULL);
-               current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+               current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
        }
 
        /* the front-end may request us not to handle breakpoints */
        if (handle_breakpoints)
        {
-               if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
+               breakpoint = breakpoint_find(target,
+                               buf_get_u32(armv4_5->pc->value, 0, 32));
+               if (breakpoint != NULL)
                {
                        uint32_t next_pc;
 
@@ -1272,8 +1254,10 @@ static int xscale_resume(struct target *target, int current,
                        }
 
                        /* send PC */
-                       xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
-                       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+                       xscale_send_u32(target,
+                                       buf_get_u32(armv4_5->pc->value, 0, 32));
+                       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
+                                       buf_get_u32(armv4_5->pc->value, 0, 32));
 
                        /* wait for and process debug entry */
                        xscale_debug_entry(target);
@@ -1316,8 +1300,9 @@ static int xscale_resume(struct target *target, int current,
        }
 
        /* send PC */
-       xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
-       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+       xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32));
+       LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+                       buf_get_u32(armv4_5->pc->value, 0, 32));
 
        target->debug_reason = DBG_REASON_NOTHALTED;
 
@@ -1354,7 +1339,7 @@ static int xscale_step_inner(struct target *target, int current,
        if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
        {
                uint32_t current_opcode, current_pc;
-               current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+               current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
                target_read_u32(target, current_pc, &current_opcode);
                LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
@@ -1399,9 +1384,12 @@ static int xscale_step_inner(struct target *target, int current,
        }
 
        /* send PC */
-       if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
+       retval = xscale_send_u32(target,
+                       buf_get_u32(armv4_5->pc->value, 0, 32));
+       if (retval != ERROR_OK)
                return retval;
-       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+       LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
+                       buf_get_u32(armv4_5->pc->value, 0, 32));
 
        target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
@@ -1425,7 +1413,7 @@ static int xscale_step(struct target *target, int current,
                uint32_t address, int handle_breakpoints)
 {
        struct arm *armv4_5 = target_to_arm(target);
-       struct breakpoint *breakpoint = target->breakpoints;
+       struct breakpoint *breakpoint = NULL;
 
        uint32_t current_pc;
        int retval;
@@ -1438,16 +1426,16 @@ static int xscale_step(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
-               buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
+               buf_set_u32(armv4_5->pc->value, 0, 32, address);
 
-       current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
        /* if we're at the reset vector, we have to simulate the step */
        if (current_pc == 0x0)
        {
                if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
                        return retval;
-               current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+               current_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
                target->debug_reason = DBG_REASON_SINGLESTEP;
                target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1457,11 +1445,13 @@ static int xscale_step(struct target *target, int current,
 
        /* the front-end may request us not to handle breakpoints */
        if (handle_breakpoints)
-               if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
-               {
-                       if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
-                               return retval;
-               }
+               breakpoint = breakpoint_find(target,
+                               buf_get_u32(armv4_5->pc->value, 0, 32));
+       if (breakpoint != NULL) {
+               retval = xscale_unset_breakpoint(target, breakpoint);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        retval = xscale_step_inner(target, current, address, handle_breakpoints);
 
@@ -1566,7 +1556,7 @@ static int xscale_deassert_reset(struct target *target)
                /* wait 300ms; 150 and 100ms were not enough */
                jtag_add_sleep(300*1000);
 
-               jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE));
+               jtag_add_runtest(2030, TAP_IDLE);
                jtag_execute_queue();
 
                /* set Hold reset, Halt mode and Trap Reset */
@@ -1623,7 +1613,7 @@ static int xscale_deassert_reset(struct target *target)
                if (retval != ERROR_OK)
                        return retval;
 
-               jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
+               jtag_add_runtest(30, TAP_IDLE);
 
                jtag_add_sleep(100000);
 
@@ -2568,7 +2558,8 @@ static int xscale_read_trace(struct target *target)
        (*trace_data_p)->next = NULL;
        (*trace_data_p)->chkpt0 = trace_buffer[256];
        (*trace_data_p)->chkpt1 = trace_buffer[257];
-       (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+       (*trace_data_p)->last_instruction =
+                       buf_get_u32(armv4_5->pc->value, 0, 32);
        (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
        (*trace_data_p)->depth = 256 - j;
 
@@ -3206,9 +3197,9 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
                return ERROR_OK;
        }
 
-       bool icache;
-       COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
-
+       bool icache = false;
+       if (strcmp(CMD_NAME, "icache") == 0)
+               icache = true;
        if (CMD_ARGC >= 1)
        {
                bool enable;
@@ -3375,7 +3366,8 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
                /* if we enable the trace buffer in fill-once
                 * mode we know the address of the first instruction */
                xscale->trace.pc_ok = 1;
-               xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+               xscale->trace.current_pc =
+                               buf_get_u32(armv4_5->pc->value, 0, 32);
        }
        else
        {
@@ -3427,7 +3419,7 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
        if (CMD_ARGC >= 2)
        {
                xscale->trace.image->base_address_set = 1;
-               COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], xscale->trace.image->base_address);
+               COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
        }
        else
        {
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)