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target: get_gdb_arch() accepts target via const pointer
[openocd.git] / src / target / xtensa / xtensa.c
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index d2ca32c1d1928d370da0a5cb8da34727c4c2bbd8..fb7748aa2d10b75016270f2091d201ce5dde208a 100644 (file)
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2646,6 +2646,7 @@ int xtensa_start_algorithm(struct target *target,
        struct xtensa_algorithm *algorithm_info = arch_info;
        int retval = ERROR_OK;
        bool usr_ps = false;
+       uint32_t newps;
 
        /* NOTE: xtensa_run_algorithm requires that each algorithm uses a software breakpoint
         * at the exit point */
@@ -2660,7 +2661,17 @@ int xtensa_start_algorithm(struct target *target,
                buf_cpy(reg->value, xtensa->algo_context_backup[i], reg->size);
        }
        /* save debug reason, it will be changed */
+       if (!algorithm_info) {
+               LOG_ERROR("BUG: arch_info not specified");
+               return ERROR_FAIL;
+       }
        algorithm_info->ctx_debug_reason = target->debug_reason;
+       if (xtensa->core_config->core_type == XT_LX) {
+               /* save PS and set to debug_level - 1 */
+               algorithm_info->ctx_ps = xtensa_reg_get(target, xtensa->eps_dbglevel_idx);
+               newps = (algorithm_info->ctx_ps & ~0xf) | (xtensa->core_config->debug.irq_level - 1);
+               xtensa_reg_set(target, xtensa->eps_dbglevel_idx, newps);
+       }
        /* write mem params */
        for (int i = 0; i < num_mem_params; i++) {
                if (mem_params[i].direction != PARAM_IN) {
@@ -2688,7 +2699,7 @@ int xtensa_start_algorithm(struct target *target,
                }
                if (memcmp(reg_params[i].reg_name, "ps", 3)) {
                        usr_ps = true;
-               } else {
+               } else if (xtensa->core_config->core_type == XT_LX) {
                        unsigned int reg_id = xtensa->eps_dbglevel_idx;
                        assert(reg_id < xtensa->core_cache->num_regs && "Attempt to access non-existing reg!");
                        reg = &xtensa->core_cache->reg_list[reg_id];
@@ -2697,7 +2708,7 @@ int xtensa_start_algorithm(struct target *target,
                reg->valid = 1;
        }
        /* ignore custom core mode if custom PS value is specified */
-       if (!usr_ps) {
+       if (!usr_ps && xtensa->core_config->core_type == XT_LX) {
                unsigned int eps_reg_idx = xtensa->eps_dbglevel_idx;
                xtensa_reg_val_t ps = xtensa_reg_get(target, eps_reg_idx);
                enum xtensa_mode core_mode = XT_PS_RING_GET(ps);
@@ -2741,7 +2752,8 @@ int xtensa_wait_algorithm(struct target *target,
                        return retval;
                LOG_TARGET_ERROR(target, "not halted %d, pc 0x%" PRIx32 ", ps 0x%" PRIx32, retval,
                        xtensa_reg_get(target, XT_REG_IDX_PC),
-                       xtensa_reg_get(target, xtensa->eps_dbglevel_idx));
+                       xtensa_reg_get(target, (xtensa->core_config->core_type == XT_LX) ?
+                               xtensa->eps_dbglevel_idx : XT_REG_IDX_PS));
                return ERROR_TARGET_TIMEOUT;
        }
        pc = xtensa_reg_get(target, XT_REG_IDX_PC);
@@ -2813,6 +2825,8 @@ int xtensa_wait_algorithm(struct target *target,
                }
        }
        target->debug_reason = algorithm_info->ctx_debug_reason;
+       if (xtensa->core_config->core_type == XT_LX)
+               xtensa_reg_set(target, xtensa->eps_dbglevel_idx, algorithm_info->ctx_ps);
 
        retval = xtensa_write_dirty_registers(target);
        if (retval != ERROR_OK)
@@ -3428,7 +3442,7 @@ void xtensa_target_deinit(struct target *target)
        free(xtensa->core_config);
 }
 
-const char *xtensa_get_gdb_arch(struct target *target)
+const char *xtensa_get_gdb_arch(const struct target *target)
 {
        return "xtensa";
 }
@@ -3445,8 +3459,8 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
        const char *parm = CMD_ARGV[0];
        unsigned int parm_len = strlen(parm);
        if ((parm_len >= 64) || (parm_len & 1)) {
-               LOG_ERROR("Invalid parameter length (%d): must be even, < 64 characters", parm_len);
-               return ERROR_FAIL;
+               command_print(CMD, "Invalid parameter length (%d): must be even, < 64 characters", parm_len);
+               return ERROR_COMMAND_ARGUMENT_INVALID;
        }
 
        uint8_t ops[32];
@@ -3466,7 +3480,7 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
         */
        int status = xtensa_write_dirty_registers(target);
        if (status != ERROR_OK) {
-               LOG_ERROR("%s: Failed to write back register cache.", target_name(target));
+               command_print(CMD, "%s: Failed to write back register cache.", target_name(target));
                return ERROR_FAIL;
        }
        xtensa_reg_val_t exccause = xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE);
@@ -3483,15 +3497,21 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
        LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
        xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */
        status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
-       if (status != ERROR_OK)
-               LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status);
-       status = xtensa_core_status_check(target);
-       if (status != ERROR_OK)
-               LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status);
+       if (status != ERROR_OK) {
+               command_print(CMD, "exec: queue error %d", status);
+       } else {
+               status = xtensa_core_status_check(target);
+               if (status != ERROR_OK)
+                       command_print(CMD, "exec: status error %d", status);
+       }
 
        /* Reread register cache and restore saved regs after instruction execution */
        if (xtensa_fetch_all_regs(target) != ERROR_OK)
-               LOG_TARGET_ERROR(target, "%s: Failed to fetch register cache (post-exec).", target_name(target));
+               command_print(CMD, "post-exec: register fetch error");
+       if (status != ERROR_OK) {
+               command_print(CMD, "post-exec: EXCCAUSE 0x%02" PRIx32,
+                       xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE));
+       }
        xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause);
        xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable);
        return status;
@@ -3514,8 +3534,8 @@ COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa)
        } else if (strcasecmp(core_name, "NX") == 0) {
                xtensa->core_config->core_type = XT_NX;
        } else {
-               LOG_ERROR("xtdef [LX|NX]\n");
-               return ERROR_COMMAND_SYNTAX_ERROR;
+               command_print(CMD, "xtdef [LX|NX]\n");
+               return ERROR_COMMAND_ARGUMENT_INVALID;
        }
        return ERROR_OK;
 }
@@ -3572,7 +3592,7 @@ COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa)
                if (!xtensa_cmd_xtopt_legal_val("excmlevel", opt_val, 1, 6))
                        return ERROR_COMMAND_ARGUMENT_INVALID;
                if (!xtensa->core_config->high_irq.enabled) {
-                       LOG_ERROR("xtopt excmlevel requires hipriints\n");
+                       command_print(CMD, "xtopt excmlevel requires hipriints\n");
                        return ERROR_COMMAND_ARGUMENT_INVALID;
                }
                xtensa->core_config->high_irq.excm_level = opt_val;
@@ -3585,7 +3605,7 @@ COMMAND_HELPER(xtensa_cmd_xtopt_do, struct xtensa *xtensa)
                                return ERROR_COMMAND_ARGUMENT_INVALID;
                }
                if (!xtensa->core_config->high_irq.enabled) {
-                       LOG_ERROR("xtopt intlevels requires hipriints\n");
+                       command_print(CMD, "xtopt intlevels requires hipriints\n");
                        return ERROR_COMMAND_ARGUMENT_INVALID;
                }
                xtensa->core_config->high_irq.level_num = opt_val;
@@ -3642,10 +3662,8 @@ COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa)
        int mem_access = 0;
        bool is_dcache = false;
 
-       if (CMD_ARGC == 0) {
-               LOG_ERROR("xtmem <type> [parameters]\n");
+       if (CMD_ARGC == 0)
                return ERROR_COMMAND_SYNTAX_ERROR;
-       }
 
        const char *mem_name = CMD_ARGV[0];
        if (strcasecmp(mem_name, "icache") == 0) {
@@ -3676,25 +3694,21 @@ COMMAND_HELPER(xtensa_cmd_xtmem_do, struct xtensa *xtensa)
                memp = &xtensa->core_config->srom;
                mem_access = XT_MEM_ACCESS_READ;
        } else {
-               LOG_ERROR("xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n");
+               command_print(CMD, "xtmem types: <icache|dcache|l2cache|l2addr|iram|irom|dram|drom|sram|srom>\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        }
 
        if (cachep) {
-               if ((CMD_ARGC != 4) && (CMD_ARGC != 5)) {
-                       LOG_ERROR("xtmem <cachetype> <linebytes> <cachebytes> <ways> [writeback]\n");
+               if (CMD_ARGC != 4 && CMD_ARGC != 5)
                        return ERROR_COMMAND_SYNTAX_ERROR;
-               }
                cachep->line_size = strtoul(CMD_ARGV[1], NULL, 0);
                cachep->size = strtoul(CMD_ARGV[2], NULL, 0);
                cachep->way_count = strtoul(CMD_ARGV[3], NULL, 0);
                cachep->writeback = ((CMD_ARGC == 5) && is_dcache) ?
                        strtoul(CMD_ARGV[4], NULL, 0) : 0;
        } else if (memp) {
-               if (CMD_ARGC != 3) {
-                       LOG_ERROR("xtmem <memtype> <baseaddr> <bytes>\n");
+               if (CMD_ARGC != 3)
                        return ERROR_COMMAND_SYNTAX_ERROR;
-               }
                struct xtensa_local_mem_region_config *memcfgp = &memp->regions[memp->count];
                memcfgp->base = strtoul(CMD_ARGV[1], NULL, 0);
                memcfgp->size = strtoul(CMD_ARGV[2], NULL, 0);
@@ -3714,10 +3728,8 @@ COMMAND_HANDLER(xtensa_cmd_xtmem)
 /* xtmpu <num FG seg> <min seg size> <lockable> <executeonly> */
 COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa)
 {
-       if (CMD_ARGC != 4) {
-               LOG_ERROR("xtmpu <num FG seg> <min seg size> <lockable> <executeonly>\n");
+       if (CMD_ARGC != 4)
                return ERROR_COMMAND_SYNTAX_ERROR;
-       }
 
        unsigned int nfgseg = strtoul(CMD_ARGV[0], NULL, 0);
        unsigned int minsegsize = strtoul(CMD_ARGV[1], NULL, 0);
@@ -3725,16 +3737,16 @@ COMMAND_HELPER(xtensa_cmd_xtmpu_do, struct xtensa *xtensa)
        unsigned int execonly = strtoul(CMD_ARGV[3], NULL, 0);
 
        if ((nfgseg > 32)) {
-               LOG_ERROR("<nfgseg> must be within [0..32]\n");
+               command_print(CMD, "<nfgseg> must be within [0..32]\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        } else if (minsegsize & (minsegsize - 1)) {
-               LOG_ERROR("<minsegsize> must be a power of 2 >= 32\n");
+               command_print(CMD, "<minsegsize> must be a power of 2 >= 32\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        } else if (lockable > 1) {
-               LOG_ERROR("<lockable> must be 0 or 1\n");
+               command_print(CMD, "<lockable> must be 0 or 1\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        } else if (execonly > 1) {
-               LOG_ERROR("<execonly> must be 0 or 1\n");
+               command_print(CMD, "<execonly> must be 0 or 1\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        }
 
@@ -3755,18 +3767,16 @@ COMMAND_HANDLER(xtensa_cmd_xtmpu)
 /* xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56> */
 COMMAND_HELPER(xtensa_cmd_xtmmu_do, struct xtensa *xtensa)
 {
-       if (CMD_ARGC != 2) {
-               LOG_ERROR("xtmmu <NIREFILLENTRIES> <NDREFILLENTRIES>\n");
+       if (CMD_ARGC != 2)
                return ERROR_COMMAND_SYNTAX_ERROR;
-       }
 
        unsigned int nirefillentries = strtoul(CMD_ARGV[0], NULL, 0);
        unsigned int ndrefillentries = strtoul(CMD_ARGV[1], NULL, 0);
        if ((nirefillentries != 16) && (nirefillentries != 32)) {
-               LOG_ERROR("<nirefillentries> must be 16 or 32\n");
+               command_print(CMD, "<nirefillentries> must be 16 or 32\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        } else if ((ndrefillentries != 16) && (ndrefillentries != 32)) {
-               LOG_ERROR("<ndrefillentries> must be 16 or 32\n");
+               command_print(CMD, "<ndrefillentries> must be 16 or 32\n");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        }
 
@@ -3789,13 +3799,13 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
        if (CMD_ARGC == 1) {
                int32_t numregs = strtoul(CMD_ARGV[0], NULL, 0);
                if ((numregs <= 0) || (numregs > UINT16_MAX)) {
-                       LOG_ERROR("xtreg <numregs>: Invalid 'numregs' (%d)", numregs);
-                       return ERROR_COMMAND_SYNTAX_ERROR;
+                       command_print(CMD, "xtreg <numregs>: Invalid 'numregs' (%d)", numregs);
+                       return ERROR_COMMAND_ARGUMENT_INVALID;
                }
                if ((xtensa->genpkt_regs_num > 0) && (numregs < (int32_t)xtensa->genpkt_regs_num)) {
-                       LOG_ERROR("xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)",
+                       command_print(CMD, "xtregs (%d) must be larger than numgenregs (%d) (if xtregfmt specified)",
                                numregs, xtensa->genpkt_regs_num);
-                       return ERROR_COMMAND_SYNTAX_ERROR;
+                       return ERROR_COMMAND_ARGUMENT_INVALID;
                }
                xtensa->total_regs_num = numregs;
                xtensa->core_regs_num = 0;
@@ -3824,17 +3834,17 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
        const char *regname = CMD_ARGV[0];
        unsigned int regnum = strtoul(CMD_ARGV[1], NULL, 0);
        if (regnum > UINT16_MAX) {
-               LOG_ERROR("<regnum> must be a 16-bit number");
+               command_print(CMD, "<regnum> must be a 16-bit number");
                return ERROR_COMMAND_ARGUMENT_INVALID;
        }
 
        if ((xtensa->num_optregs + xtensa->core_regs_num) >= xtensa->total_regs_num) {
                if (xtensa->total_regs_num)
-                       LOG_ERROR("'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)",
+                       command_print(CMD, "'xtreg %s 0x%04x': Too many registers (%d expected, %d core %d extended)",
                                regname, regnum,
                                xtensa->total_regs_num, xtensa->core_regs_num, xtensa->num_optregs);
                else
-                       LOG_ERROR("'xtreg %s 0x%04x': Number of registers unspecified",
+                       command_print(CMD, "'xtreg %s 0x%04x': Number of registers unspecified",
                                regname, regnum);
                return ERROR_FAIL;
        }
@@ -3914,7 +3924,7 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
                                idx = XT_NX_REG_IDX_MESRCLR;
                        if (idx < XT_NX_REG_IDX_NUM) {
                                if (xtensa->nx_reg_idx[idx] != 0) {
-                                       LOG_ERROR("nx_reg_idx[%d] previously set to %d",
+                                       command_print(CMD, "nx_reg_idx[%d] previously set to %d",
                                                idx, xtensa->nx_reg_idx[idx]);
                                        return ERROR_FAIL;
                                }
@@ -3961,9 +3971,9 @@ COMMAND_HELPER(xtensa_cmd_xtregfmt_do, struct xtensa *xtensa)
                                if ((numgregs <= 0) ||
                                        ((numgregs > xtensa->total_regs_num) &&
                                        (xtensa->total_regs_num > 0))) {
-                                       LOG_ERROR("xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
+                                       command_print(CMD, "xtregfmt: if specified, numgregs (%d) must be <= numregs (%d)",
                                                numgregs, xtensa->total_regs_num);
-                                       return ERROR_COMMAND_SYNTAX_ERROR;
+                                       return ERROR_COMMAND_ARGUMENT_INVALID;
                                }
                                xtensa->genpkt_regs_num = numgregs;
                        }
@@ -4079,7 +4089,7 @@ COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa)
                        "%-12" PRIu64 "%s",
                        result.value,
                        result.overflow ? " (overflow)" : "");
-               LOG_INFO("%s", result_buf);
+               command_print(CMD, "%s", result_buf);
        }
 
        return ERROR_OK;
@@ -4329,21 +4339,21 @@ COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname
        }
 
        memsz = trace_config.memaddr_end - trace_config.memaddr_start + 1;
-       LOG_INFO("Total trace memory: %d words", memsz);
+       command_print(CMD, "Total trace memory: %d words", memsz);
        if ((trace_config.addr &
                        ((TRAXADDR_TWRAP_MASK << TRAXADDR_TWRAP_SHIFT) | TRAXADDR_TWSAT)) == 0) {
                /*Memory hasn't overwritten itself yet. */
                wmem = trace_config.addr & TRAXADDR_TADDR_MASK;
-               LOG_INFO("...but trace is only %d words", wmem);
+               command_print(CMD, "...but trace is only %d words", wmem);
                if (wmem < memsz)
                        memsz = wmem;
        } else {
                if (trace_config.addr & TRAXADDR_TWSAT) {
-                       LOG_INFO("Real trace is many times longer than that (overflow)");
+                       command_print(CMD, "Real trace is many times longer than that (overflow)");
                } else {
                        uint32_t trc_sz = (trace_config.addr >> TRAXADDR_TWRAP_SHIFT) & TRAXADDR_TWRAP_MASK;
                        trc_sz = (trc_sz * memsz) + (trace_config.addr & TRAXADDR_TADDR_MASK);
-                       LOG_INFO("Real trace is %d words, but the start has been truncated.", trc_sz);
+                       command_print(CMD, "Real trace is %d words, but the start has been truncated.", trc_sz);
                }
        }
 
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Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)