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target: get_gdb_arch() accepts target via const pointer
[openocd.git] / src / target / xtensa / xtensa.h
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index fd03f07f85375ff10dcf57eab806063e5d4158bb..a220021a68d9edf805d5e9edd98c5ce9e8ade468 100644 (file)
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -35,6 +35,7 @@
 
 #define XT_ISNS_SZ_MAX                          3
 
+/* PS register bits (LX) */
 #define XT_PS_RING(_v_)                         ((uint32_t)((_v_) & 0x3) << 6)
 #define XT_PS_RING_MSK                          (0x3 << 6)
 #define XT_PS_RING_GET(_v_)                     (((_v_) >> 6) & 0x3)
@@ -42,6 +43,31 @@
 #define XT_PS_OWB_MSK                           (0xF << 8)
 #define XT_PS_WOE_MSK                           BIT(18)
 
+/* PS register bits (NX) */
+#define XT_PS_DIEXC_MSK                         BIT(2)
+
+/* MS register bits (NX) */
+#define XT_MS_DE_MSK                            BIT(5)
+#define XT_MS_DISPST_MSK                        (0x1f)
+#define XT_MS_DISPST_DBG                        (0x10)
+
+/* WB register bits (NX) */
+#define XT_WB_P_SHIFT                           (0)
+#define XT_WB_P_MSK                             (0x7U << XT_WB_P_SHIFT)
+#define XT_WB_C_SHIFT                           (4)
+#define XT_WB_C_MSK                             (0x7U << XT_WB_C_SHIFT)
+#define XT_WB_N_SHIFT                           (8)
+#define XT_WB_N_MSK                             (0x7U << XT_WB_N_SHIFT)
+#define XT_WB_S_SHIFT                           (30)
+#define XT_WB_S_MSK                             (0x3U << XT_WB_S_SHIFT)
+
+/* IBREAKC register bits (NX) */
+#define XT_IBREAKC_FB                           (0x80000000)
+
+/* Definitions for imprecise exception registers (NX) */
+#define XT_IMPR_EXC_MSK                         (0x00000013)
+#define XT_MESRCLR_IMPR_EXC_MSK                 (0x00000090)
+
 #define XT_LOCAL_MEM_REGIONS_NUM_MAX            8
 
 #define XT_AREGS_NUM_MAX                        64
@@ -79,6 +105,7 @@ struct xtensa_keyval_info_s {
 enum xtensa_type {
        XT_UNDEF = 0,
        XT_LX,
+       XT_NX,
 };
 
 struct xtensa_cache_config {
@@ -167,6 +194,17 @@ enum xtensa_stepping_isr_mode {
        XT_STEPPING_ISR_ON,             /* interrupts are enabled during stepping */
 };
 
+enum xtensa_nx_reg_idx {
+       XT_NX_REG_IDX_IBREAKC0 = 0,
+       XT_NX_REG_IDX_WB,
+       XT_NX_REG_IDX_MS,
+       XT_NX_REG_IDX_IEVEC,            /* IEVEC, IEEXTERN, and MESR must be contiguous */
+       XT_NX_REG_IDX_IEEXTERN,
+       XT_NX_REG_IDX_MESR,
+       XT_NX_REG_IDX_MESRCLR,
+       XT_NX_REG_IDX_NUM
+};
+
 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
 enum xtensa_mode {
        XT_MODE_RING0,
@@ -184,6 +222,17 @@ struct xtensa_sw_breakpoint {
        uint8_t insn_sz;        /* 2 or 3 bytes */
 };
 
+/**
+ * Xtensa algorithm data.
+ */
+struct xtensa_algorithm {
+       /** User can set this to specify which core mode algorithm should be run in. */
+       enum xtensa_mode core_mode;
+       /** Used internally to backup and restore core state. */
+       enum target_debug_reason ctx_debug_reason;
+       xtensa_reg_val_t ctx_ps;
+};
+
 #define XTENSA_COMMON_MAGIC 0x54E4E555U
 
 /**
@@ -232,6 +281,8 @@ struct xtensa {
        uint8_t come_online_probes_num;
        bool proc_syscall;
        bool halt_request;
+       uint32_t nx_stop_cause;
+       uint32_t nx_reg_idx[XT_NX_REG_IDX_NUM];
        struct xtensa_keyval_info_s scratch_ars[XT_AR_SCRATCH_NUM];
        bool regs_fetched;      /* true after first register fetch completed successfully */
 };
@@ -273,24 +324,24 @@ static inline bool xtensa_data_addr_valid(struct target *target, uint32_t addr)
        return false;
 }
 
-static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, unsigned int reg, uint8_t *data)
+static inline int xtensa_queue_dbg_reg_read(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint8_t *data)
 {
        struct xtensa_debug_module *dm = &xtensa->dbg_mod;
 
        if (!xtensa->core_config->trace.enabled &&
-               (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
+               (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
                LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
                return ERROR_FAIL;
        }
        return dm->dbg_ops->queue_reg_read(dm, reg, data);
 }
 
-static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
+static inline int xtensa_queue_dbg_reg_write(struct xtensa *xtensa, enum xtensa_dm_reg reg, uint32_t data)
 {
        struct xtensa_debug_module *dm = &xtensa->dbg_mod;
 
        if (!xtensa->core_config->trace.enabled &&
-               (reg <= NARADR_MEMADDREND || (reg >= NARADR_PMG && reg <= NARADR_PMSTAT7))) {
+               (reg <= XDMREG_MEMADDREND || (reg >= XDMREG_PMG && reg <= XDMREG_PMSTAT7))) {
                LOG_ERROR("Can not access %u reg when Trace Port option disabled!", reg);
                return ERROR_FAIL;
        }
@@ -355,8 +406,23 @@ int xtensa_breakpoint_add(struct target *target, struct breakpoint *breakpoint);
 int xtensa_breakpoint_remove(struct target *target, struct breakpoint *breakpoint);
 int xtensa_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
 int xtensa_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
+int xtensa_start_algorithm(struct target *target,
+       int num_mem_params, struct mem_param *mem_params,
+       int num_reg_params, struct reg_param *reg_params,
+       target_addr_t entry_point, target_addr_t exit_point,
+       void *arch_info);
+int xtensa_wait_algorithm(struct target *target,
+       int num_mem_params, struct mem_param *mem_params,
+       int num_reg_params, struct reg_param *reg_params,
+       target_addr_t exit_point, unsigned int timeout_ms,
+       void *arch_info);
+int xtensa_run_algorithm(struct target *target,
+       int num_mem_params, struct mem_param *mem_params,
+       int num_reg_params, struct reg_param *reg_params,
+       target_addr_t entry_point, target_addr_t exit_point,
+       unsigned int timeout_ms, void *arch_info);
 void xtensa_set_permissive_mode(struct target *target, bool state);
-const char *xtensa_get_gdb_arch(struct target *target);
+const char *xtensa_get_gdb_arch(const struct target *target);
 int xtensa_gdb_query_custom(struct target *target, const char *packet, char **response_p);
 
 COMMAND_HELPER(xtensa_cmd_xtdef_do, struct xtensa *xtensa);
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