target.cfg: TAP id for Hilscher netX 500

[openocd.git] / tcl / board / at91sam9g20-ek.cfg

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index c9deb144b0fe87ee1f94a495ea167d533366839a..6e8a193469d918b12ccacfaeb6ab80aeeb374186 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -41,8 +41,8 @@ target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNA
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
 # Both areas are 16 kB long.
 
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
 
 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
 # AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
@@ -62,7 +62,7 @@ proc read_register {register} {
 }
 
 proc at91sam9g20_init { } {
-       
+
        # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
        # a number of steps that must be carefully performed.  The process outline below follows the
        # recommended procedure outlined in the AT91SAM9G20 technical manual.
@@ -94,7 +94,7 @@ proc at91sam9g20_init { } {
 
        mww 0xfffffc30 0x00000101
        while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-       
+
        # Now change PMC_MCKR register to select PLLA.
        # Wait for MCKRDY signal from PMC_SR to assert.