target/xtensa: avoid IHI for writes to non-executable memory

[openocd.git] / tcl / target / ixp42x.cfg

diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg
index 3f86e357b9557eb80fddc6cb8546c1a365020766..5c8e9032156f593ac0e2fb2ed86c11e242a00d6b 100644 (file)
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #xscale ixp42x CPU
 
 if { [info exists CHIPNAME] } {
@@ -66,17 +68,17 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
-# REFRESH: refresh counter reload value (integer) 
-# CASLAT: 2 or 3 
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3
 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {
        2 {
-           set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
+           set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ]
            set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
        }
        3 {
-           set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
+           set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ]
            set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
        }
        default { error [format "unsupported cas latency \"%s\" " $CASLAT] }