tcl: replace '-ctibase' with '-baseaddr'
[openocd.git] / tcl / target / renesas_rcar_gen3.cfg
index 2c478b2685a67446df1bdb5f93203f3f5b77818b..5738d371c6eeb2267ef88a2cf061fd52bf7a3b88 100644 (file)
@@ -76,7 +76,7 @@ switch $_soc {
                set _boot_core CA53
        }
        default {
-               echo "'$_soc' is invalid!"
+               error "'$_soc' is invalid!"
        }
 }
 
@@ -122,7 +122,7 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
                set _TARGETNAME $_CHIPNAME.$core_name.$_core
                set _CTINAME $_TARGETNAME.cti
                cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
-                       -ctibase [lindex $ctibase $_core]
+                       -baseaddr [lindex $ctibase $_core]
                set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
                        -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
                if { $_core == 0  && $boot == 1 } {
@@ -140,7 +140,7 @@ proc setup_cr7 {dbgbase ctibase boot} {
        global _DAPNAME
        set _TARGETNAME $_CHIPNAME.r7
        set _CTINAME $_TARGETNAME.cti
-       cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -ctibase $ctibase
+       cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
        set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
                -ap-num 1 -dbgbase $dbgbase"
        if { $boot == 1 } {
@@ -166,4 +166,6 @@ if { [string equal $_boot_core CA57] } {
        setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 }
 
+source [find target/renesas_rcar_reset_common.cfg]
+
 eval "target smp $smp_targets"

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