X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Fflash%2Fnor%2Fat91sam3.c;h=dac901ecd54d5e20422169b54dc910ff0a5b5ce9;hb=16b6b5e7a86353dbc0c4823fe3d772c0faca7c1c;hp=1194e25f1a7e840c24ffaa4055144fa4f3b87dc1;hpb=d9dc604a4d790f557a7ba502babdabffa27eaa17;p=openocd.git diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 1194e25f1a..dac901ecd5 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -2,6 +2,10 @@ * Copyright (C) 2009 by Duane Ellis * * openocd@duaneellis.com * * * + * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) * + * olaf@uni-paderborn.de * + * * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -58,15 +62,19 @@ #include "imp.h" -#include "at91sam3.h" -#include #include #define REG_NAME_WIDTH (12) +// at91sam3u series (has one or two flash banks) +#define FLASH_BANK0_BASE_U 0x00080000 +#define FLASH_BANK1_BASE_U 0x00100000 -#define FLASH_BANK0_BASE 0x00080000 -#define FLASH_BANK1_BASE 0x00100000 +// at91sam3s series (has always one flash bank) +#define FLASH_BANK_BASE_S 0x00400000 + +// at91sam3n series (has always one flash bank) +#define FLASH_BANK_BASE_N 0x00400000 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page @@ -93,6 +101,8 @@ #define offset_EFC_FRR 12 +extern struct flash_driver at91sam3_flash; + static float _tomhz(uint32_t freq_hz) { @@ -157,6 +167,15 @@ struct sam3_cfg { uint32_t PMC_FSPR; }; +/* + * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011 + * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes + * the flash wait state (FWS) should be set to 6. It seems like that the + * cause of the problem is not the flash itself, but the flash write + * buffer. Ie the wait states have to be set before writing into the + * buffer. + * Tested and confirmed with SAM3N and SAM3U + */ struct sam3_bank_private { int probed; @@ -173,6 +192,7 @@ struct sam3_bank_private { unsigned bank_number; uint32_t controller_address; uint32_t base_address; + uint32_t flash_wait_states; bool present; unsigned size_bytes; unsigned nsectors; @@ -211,8 +231,6 @@ struct sam3_chip { struct sam3_chip_details details; struct target *target; struct sam3_cfg cfg; - - struct membuf *mbuf; }; @@ -255,15 +273,644 @@ get_current_sam3(struct command_context *cmd_ctx) } -// these are used to *initialize* the "pChip->details" structure. -static const struct sam3_chip_details all_sam3_details[] = { +// these are used to *initialize* the "pChip->details" structure. +static const struct sam3_chip_details all_sam3_details[] = { + // Start at91sam3u* series + { + .chipid_cidr = 0x28100960, + .name = "at91sam3u4e", + .total_flash_size = 256 * 1024, + .total_sram_size = 52 * 1024, + .n_gpnvms = 3, + .n_banks = 2, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif +// .bank[0] = { + { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, + +// .bank[1] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 1, + .base_address = FLASH_BANK1_BASE_U, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, + }, + }, + + { + .chipid_cidr = 0x281a0760, + .name = "at91sam3u2e", + .total_flash_size = 128 * 1024, + .total_sram_size = 36 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif +// .bank[0] = { + { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + { + .chipid_cidr = 0x28190560, + .name = "at91sam3u1e", + .total_flash_size = 64 * 1024, + .total_sram_size = 20 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + +// .bank[0] = { + { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 64 * 1024, + .nsectors = 8, + .sector_size = 8192, + .page_size = 256, + }, + +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + + { + .chipid_cidr = 0x28000960, + .name = "at91sam3u4c", + .total_flash_size = 256 * 1024, + .total_sram_size = 52 * 1024, + .n_gpnvms = 3, + .n_banks = 2, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif + { + { +// .bank[0] = { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 1, + .base_address = FLASH_BANK1_BASE_U, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, + }, + }, + + { + .chipid_cidr = 0x280a0760, + .name = "at91sam3u2c", + .total_flash_size = 128 * 1024, + .total_sram_size = 36 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + { + .chipid_cidr = 0x28090560, + .name = "at91sam3u1c", + .total_flash_size = 64 * 1024, + .total_sram_size = 20 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_U, + .controller_address = 0x400e0800, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 64 * 1024, + .nsectors = 8, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + + // Start at91sam3s* series + + // Note: The preliminary at91sam3s datasheet says on page 302 + // that the flash controller is at address 0x400E0800. + // This is _not_ the case, the controller resides at address 0x400e0a0. + { + .chipid_cidr = 0x28A00960, + .name = "at91sam3s4c", + .total_flash_size = 256 * 1024, + .total_sram_size = 48 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 32, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + + { + .chipid_cidr = 0x28900960, + .name = "at91sam3s4b", + .total_flash_size = 256 * 1024, + .total_sram_size = 48 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 32, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28800960, + .name = "at91sam3s4a", + .total_flash_size = 256 * 1024, + .total_sram_size = 48 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 32, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28AA0760, + .name = "at91sam3s2c", + .total_flash_size = 128 * 1024, + .total_sram_size = 32 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x289A0760, + .name = "at91sam3s2b", + .total_flash_size = 128 * 1024, + .total_sram_size = 32 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x288A0760, + .name = "at91sam3s2a", + .total_flash_size = 128 * 1024, + .total_sram_size = 32 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 128 * 1024, + .nsectors = 16, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28A90560, + .name = "at91sam3s1c", + .total_flash_size = 64 * 1024, + .total_sram_size = 16 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 64 * 1024, + .nsectors = 8, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28990560, + .name = "at91sam3s1b", + .total_flash_size = 64 * 1024, + .total_sram_size = 16 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 64 * 1024, + .nsectors = 8, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28890560, + .name = "at91sam3s1a", + .total_flash_size = 64 * 1024, + .total_sram_size = 16 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +// .bank[0] = { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 64 * 1024, + .nsectors = 8, + .sector_size = 8192, + .page_size = 256, + }, +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + + // Start at91sam3n* series + { + .chipid_cidr = 0x29540960, + .name = "at91sam3n4c", + .total_flash_size = 256 * 1024, + .total_sram_size = 24 * 1024, + .n_gpnvms = 3, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif +// .bank[0] = { + { + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 16, + .sector_size = 16384, + .page_size = 256, + }, + +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + { - .chipid_cidr = 0x28100960, - .name = "at91sam3u4e", + .chipid_cidr = 0x29440960, + .name = "at91sam3n4b", .total_flash_size = 256 * 1024, - .total_sram_size = 52 * 1024, + .total_sram_size = 24 * 1024, .n_gpnvms = 3, - .n_banks = 2, + .n_banks = 1, // System boots at address 0x0 // gpnvm[1] = selects boot code @@ -287,38 +934,80 @@ static const struct sam3_chip_details all_sam3_details[] = { .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 128 * 1024, + .size_bytes = 256 * 1024, .nsectors = 16, - .sector_size = 8192, + .sector_size = 16384, .page_size = 256, }, // .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + + { + .chipid_cidr = 0x29340960, + .name = "at91sam3n4a", + .total_flash_size = 256 * 1024, + .total_sram_size = 24 * 1024, + .n_gpnvms = 3, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif +// .bank[0] = { + { { .probed = 0, .pChip = NULL, .pBank = NULL, - .bank_number = 1, - .base_address = FLASH_BANK1_BASE, - .controller_address = 0x400e0a00, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 128 * 1024, + .size_bytes = 256 * 1024, .nsectors = 16, - .sector_size = 8192, + .sector_size = 16384, .page_size = 256, }, + +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, }, }, { - .chipid_cidr = 0x281a0760, - .name = "at91sam3u2e", + .chipid_cidr = 0x29590760, + .name = "at91sam3n2c", .total_flash_size = 128 * 1024, - .total_sram_size = 36 * 1024, - .n_gpnvms = 2, + .total_sram_size = 16 * 1024, + .n_gpnvms = 3, .n_banks = 1, // System boots at address 0x0 @@ -329,6 +1018,13 @@ static const struct sam3_chip_details all_sam3_details[] = { // boot is via FLASH // Selection is via gpnvm[2] // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif // .bank[0] = { { { @@ -336,28 +1032,31 @@ static const struct sam3_chip_details all_sam3_details[] = { .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, .size_bytes = 128 * 1024, - .nsectors = 16, - .sector_size = 8192, + .nsectors = 8, + .sector_size = 16384, .page_size = 256, }, -// .bank[1] = { + +// .bank[1] = { { - .present = 0, + .present = 0, .probed = 0, .bank_number = 1, }, }, }, + { - .chipid_cidr = 0x28190560, - .name = "at91sam3u1e", - .total_flash_size = 64 * 1024, - .total_sram_size = 20 * 1024, - .n_gpnvms = 2, + .chipid_cidr = 0x29490760, + .name = "at91sam3n2b", + .total_flash_size = 128 * 1024, + .total_sram_size = 16 * 1024, + .n_gpnvms = 3, .n_banks = 1, // System boots at address 0x0 @@ -369,7 +1068,12 @@ static const struct sam3_chip_details all_sam3_details[] = { // Selection is via gpnvm[2] // endif // - + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif // .bank[0] = { { { @@ -377,18 +1081,19 @@ static const struct sam3_chip_details all_sam3_details[] = { .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 64 * 1024, - .nsectors = 8, - .sector_size = 8192, + .size_bytes = 128 * 1024, + .nsectors = 8, + .sector_size = 16384, .page_size = 256, }, // .bank[1] = { { - .present = 0, + .present = 0, .probed = 0, .bank_number = 1, }, @@ -396,12 +1101,12 @@ static const struct sam3_chip_details all_sam3_details[] = { }, { - .chipid_cidr = 0x28000960, - .name = "at91sam3u4c", - .total_flash_size = 256 * 1024, - .total_sram_size = 52 * 1024, + .chipid_cidr = 0x29390760, + .name = "at91sam3n2a", + .total_flash_size = 128 * 1024, + .total_sram_size = 16 * 1024, .n_gpnvms = 3, - .n_banks = 2, + .n_banks = 1, // System boots at address 0x0 // gpnvm[1] = selects boot code @@ -418,44 +1123,87 @@ static const struct sam3_chip_details all_sam3_details[] = { // else // Bank1 is the boot rom // endif +// .bank[0] = { { { -// .bank[0] = { .probed = 0, .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, .size_bytes = 128 * 1024, - .nsectors = 16, - .sector_size = 8192, + .nsectors = 8, + .sector_size = 16384, .page_size = 256, }, + // .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, + }, + }, + + { + .chipid_cidr = 0x29580560, + .name = "at91sam3n1c", + .total_flash_size = 64 * 1024, + .total_sram_size = 8 * 1024, + .n_gpnvms = 3, + .n_banks = 1, + + // System boots at address 0x0 + // gpnvm[1] = selects boot code + // if gpnvm[1] == 0 + // boot is via "SAMBA" (rom) + // else + // boot is via FLASH + // Selection is via gpnvm[2] + // endif + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif +// .bank[0] = { + { { .probed = 0, .pChip = NULL, .pBank = NULL, - .bank_number = 1, - .base_address = FLASH_BANK1_BASE, - .controller_address = 0x400e0a00, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 128 * 1024, - .nsectors = 16, - .sector_size = 8192, + .size_bytes = 64 * 1024, + .nsectors = 4, + .sector_size = 16384, .page_size = 256, }, + +// .bank[1] = { + { + .present = 0, + .probed = 0, + .bank_number = 1, + }, }, }, { - .chipid_cidr = 0x280a0760, - .name = "at91sam3u2c", - .total_flash_size = 128 * 1024, - .total_sram_size = 36 * 1024, - .n_gpnvms = 2, + .chipid_cidr = 0x29480560, + .name = "at91sam3n1b", + .total_flash_size = 64 * 1024, + .total_sram_size = 8 * 1024, + .n_gpnvms = 3, .n_banks = 1, // System boots at address 0x0 @@ -466,35 +1214,45 @@ static const struct sam3_chip_details all_sam3_details[] = { // boot is via FLASH // Selection is via gpnvm[2] // endif - { + // + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif // .bank[0] = { + { { .probed = 0, .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 128 * 1024, - .nsectors = 16, - .sector_size = 8192, + .size_bytes = 64 * 1024, + .nsectors = 4, + .sector_size = 16384, .page_size = 256, }, + // .bank[1] = { { - .present = 0, + .present = 0, .probed = 0, .bank_number = 1, }, }, }, + { - .chipid_cidr = 0x28090560, - .name = "at91sam3u1c", + .chipid_cidr = 0x29380560, + .name = "at91sam3n1a", .total_flash_size = 64 * 1024, - .total_sram_size = 20 * 1024, - .n_gpnvms = 2, + .total_sram_size = 8 * 1024, + .n_gpnvms = 3, .n_banks = 1, // System boots at address 0x0 @@ -506,28 +1264,34 @@ static const struct sam3_chip_details all_sam3_details[] = { // Selection is via gpnvm[2] // endif // - - { + // NOTE: banks 0 & 1 switch places + // if gpnvm[2] == 0 + // Bank0 is the boot rom + // else + // Bank1 is the boot rom + // endif // .bank[0] = { + { { .probed = 0, .pChip = NULL, .pBank = NULL, .bank_number = 0, - .base_address = FLASH_BANK0_BASE, - .controller_address = 0x400e0800, + .base_address = FLASH_BANK_BASE_N, + .controller_address = 0x400e0A00, + .flash_wait_states = 6, /* workaround silicon bug */ .present = 1, - .size_bytes = 64 * 1024, - .nsectors = 8, - .sector_size = 8192, + .size_bytes = 64 * 1024, + .nsectors = 4, + .sector_size = 16384, .page_size = 256, }, + // .bank[1] = { { - .present = 0, + .present = 0, .probed = 0, .bank_number = 1, - }, }, }, @@ -1000,20 +1764,6 @@ FLASHD_Lock(struct sam3_bank_private *pPrivate, /****** END SAM3 CODE ********/ /* begin helpful debug code */ - -static void -sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...) -{ - va_list ap; - va_start(ap,fmt); - if (pChip->mbuf == NULL) { - return; - } - - membuf_vsprintf(pChip->mbuf, fmt, ap); - va_end(ap); -} - // print the fieldname, the field value, in dec & hex, and return field value static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip, @@ -1038,7 +1788,7 @@ sam3_reg_fieldname(struct sam3_chip *pChip, } // show the basics - sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ", + LOG_USER_N("\t%*s: %*d [0x%0*x] ", REG_NAME_WIDTH, regname, dwidth, v, hwidth, v); @@ -1173,16 +1923,16 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip) uint32_t rcen; v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1); - sam3_sprintf(pChip, "(main xtal enabled: %s)\n", + LOG_USER("(main xtal enabled: %s)", _yes_or_no(v)); v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1); - sam3_sprintf(pChip, "(main osc bypass: %s)\n", + LOG_USER("(main osc bypass: %s)", _yes_or_no(v)); - rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1); - sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n", + rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1); + LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen)); v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3); - sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n", + LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]); pChip->cfg.rc_freq = 0; @@ -1190,6 +1940,7 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip) switch (v) { default: pChip->cfg.rc_freq = 0; + break; case 0: pChip->cfg.rc_freq = 4 * 1000 * 1000; break; @@ -1203,14 +1954,14 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip) } v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8); - sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n", + LOG_USER("(startup clks, time= %f uSecs)", ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq))); v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1); - sam3_sprintf(pChip, "(mainosc source: %s)\n", + LOG_USER("(mainosc source: %s)", v ? "external xtal" : "internal RC"); v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1); - sam3_sprintf(pChip, "(clock failure enabled: %s)\n", + LOG_USER("(clock failure enabled: %s)", _yes_or_no(v)); } @@ -1224,19 +1975,19 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip) const char *cp; sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5); - sam3_sprintf(pChip,"\n"); + LOG_USER_N("\n"); v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3); - sam3_sprintf(pChip, "%s\n", eproc_names[v]); + LOG_USER("%s", eproc_names[v]); v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4); - sam3_sprintf(pChip, "%s\n", nvpsize[v]); + LOG_USER("%s", nvpsize[v]); v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4); - sam3_sprintf(pChip, "%s\n", nvpsize2[v]); + LOG_USER("%s", nvpsize2[v]); v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4); - sam3_sprintf(pChip, "%s\n", sramsize[ v ]); + LOG_USER("%s", sramsize[ v ]); v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8); cp = _unknown; @@ -1247,13 +1998,13 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip) } } - sam3_sprintf(pChip, "%s\n", cp); + LOG_USER("%s", cp); v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3); - sam3_sprintf(pChip, "%s\n", nvptype[ v ]); + LOG_USER("%s", nvptype[ v ]); v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1); - sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v)); + LOG_USER("(exists: %s)", _yes_or_no(v)); } static void @@ -1263,14 +2014,14 @@ sam3_explain_ckgr_mcfr(struct sam3_chip *pChip) v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1); - sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v)); + LOG_USER("(main ready: %s)", _yes_or_no(v)); v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16); v = (v * pChip->cfg.slow_freq) / 16; pChip->cfg.mainosc_freq = v; - sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n", + LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)", _tomhz(v), pChip->cfg.slow_freq / 1000, pChip->cfg.slow_freq % 1000); @@ -1283,17 +2034,17 @@ sam3_explain_ckgr_plla(struct sam3_chip *pChip) uint32_t mula,diva; diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8); - sam3_sprintf(pChip,"\n"); + LOG_USER_N("\n"); mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11); - sam3_sprintf(pChip,"\n"); + LOG_USER_N("\n"); pChip->cfg.plla_freq = 0; if (mula == 0) { - sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n"); + LOG_USER("\tPLLA Freq: (Disabled,mula = 0)"); } else if (diva == 0) { - sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n"); + LOG_USER("\tPLLA Freq: (Disabled,diva = 0)"); } else if (diva == 1) { pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1)); - sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n", + LOG_USER("\tPLLA Freq: %3.03f MHz", _tomhz(pChip->cfg.plla_freq)); } } @@ -1334,7 +2085,7 @@ sam3_explain_mckr(struct sam3_chip *pChip) break; } - sam3_sprintf(pChip, "%s (%3.03f Mhz)\n", + LOG_USER("%s (%3.03f Mhz)", cp, _tomhz(fin)); pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3); @@ -1342,6 +2093,7 @@ sam3_explain_mckr(struct sam3_chip *pChip) case 0: pdiv = 1; cp = "selected clock"; + break; case 1: pdiv = 2; cp = "clock/2"; @@ -1374,14 +2126,14 @@ sam3_explain_mckr(struct sam3_chip *pChip) assert(0); break; } - sam3_sprintf(pChip, "(%s)\n", cp); + LOG_USER("(%s)", cp); fin = fin / pdiv; // sam3 has a *SINGLE* clock - // other at91 series parts have divisors for these. pChip->cfg.cpu_freq = fin; pChip->cfg.mclk_freq = fin; pChip->cfg.fclk_freq = fin; - sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n", + LOG_USER("\t\tResult CPU Freq: %3.03f", _tomhz(fin)); } @@ -1417,7 +2169,7 @@ sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList) // By using prototypes - we can detect what would // be casting errors. - return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset)); + return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset)); } @@ -1471,7 +2223,7 @@ sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here) // calculate where this one go.. // it is "possibly" this register. - pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset)); + pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset)); // well? Is it this register if (pPossible == goes_here) { @@ -1501,7 +2253,7 @@ sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here) r = target_read_u32(pChip->target, pReg->address, goes_here); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n", + LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d", pReg->name, (unsigned)(pReg->address), r); } return r; @@ -1520,7 +2272,7 @@ sam3_ReadAllRegs(struct sam3_chip *pChip) r = sam3_ReadThisReg(pChip, sam3_get_reg_ptr(&(pChip->cfg), pReg)); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n", + LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d", pReg->name, ((unsigned)(pReg->address)), r); return r; } @@ -1538,15 +2290,12 @@ sam3_GetInfo(struct sam3_chip *pChip) const struct sam3_reg_list *pReg; uint32_t regval; - membuf_reset(pChip->mbuf); - - pReg = &(sam3_all_regs[0]); while (pReg->name) { // display all regs LOG_DEBUG("Start: %s", pReg->name); regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg); - sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n", + LOG_USER("%*s: [0x%08x] -> 0x%08x", REG_NAME_WIDTH, pReg->name, pReg->address, @@ -1557,14 +2306,14 @@ sam3_GetInfo(struct sam3_chip *pChip) LOG_DEBUG("End: %s", pReg->name); pReg++; } - sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq)); - sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq)); - sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq)); - sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq)); - sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq)); + LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq)); + LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq)); + LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq)); + LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq)); + LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq)); - sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n", + LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x", pChip->cfg.unique_id[0], pChip->cfg.unique_id[1], pChip->cfg.unique_id[2], @@ -1586,7 +2335,7 @@ sam3_erase_check(struct flash_bank *bank) return ERROR_TARGET_NOT_HALTED; } if (0 == bank->num_sectors) { - LOG_ERROR("Target: not supported/not probed\n"); + LOG_ERROR("Target: not supported/not probed"); return ERROR_FAIL; } @@ -1664,33 +2413,42 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command) // assumption is this runs at 32khz pChip->cfg.slow_freq = 32768; pChip->probed = 0; - pChip->mbuf = membuf_new(); - if (!(pChip->mbuf)) { - LOG_ERROR("no memory"); - return ERROR_FAIL; - } } switch (bank->base) { default: - LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)", + LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \ + [at91sam3u series] or 0x%08x [at91sam3s series] or \ + 0x%08x [at91sam3n series])", ((unsigned int)(bank->base)), - ((unsigned int)(FLASH_BANK0_BASE)), - ((unsigned int)(FLASH_BANK1_BASE))); + ((unsigned int)(FLASH_BANK0_BASE_U)), + ((unsigned int)(FLASH_BANK1_BASE_U)), + ((unsigned int)(FLASH_BANK_BASE_S)), + ((unsigned int)(FLASH_BANK_BASE_N))); return ERROR_FAIL; break; - case FLASH_BANK0_BASE: + + // at91sam3u series + case FLASH_BANK0_BASE_U: bank->driver_priv = &(pChip->details.bank[0]); bank->bank_number = 0; pChip->details.bank[0].pChip = pChip; pChip->details.bank[0].pBank = bank; break; - case FLASH_BANK1_BASE: + case FLASH_BANK1_BASE_U: bank->driver_priv = &(pChip->details.bank[1]); bank->bank_number = 1; pChip->details.bank[1].pChip = pChip; pChip->details.bank[1].pBank = bank; break; + + /* at91sam3s and at91sam3n series */ + case FLASH_BANK_BASE_S: + bank->driver_priv = &(pChip->details.bank[0]); + bank->bank_number = 0; + pChip->details.bank[0].pChip = pChip; + pChip->details.bank[0].pBank = bank; + break; } // we initialize after probing. @@ -1702,16 +2460,14 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate) { const struct sam3_chip_details *pDetails; struct sam3_chip *pChip; - void *vp; struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS]; - unsigned x; - const char *cp; LOG_DEBUG("Begin"); pDetails = all_sam3_details; while (pDetails->name) { - if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) { + // Compare cidr without version bits + if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0)) { break; } else { pDetails++; @@ -1721,16 +2477,9 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate) LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)", (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR)); // Help the victim, print details about the chip - membuf_reset(pPrivate->pChip->mbuf); - membuf_sprintf(pPrivate->pChip->mbuf, - "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n", + LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows", pPrivate->pChip->cfg.CHIPID_CIDR); sam3_explain_chipid_cidr(pPrivate->pChip); - cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp); - while (cp) { - LOG_INFO("%s", cp); - cp = membuf_strtok(NULL, "\n", &vp); - } return ERROR_FAIL; } @@ -1787,7 +2536,7 @@ _sam3_probe(struct flash_bank *bank, int noise) pPrivate = get_sam3_bank_private(bank); if (!pPrivate) { - LOG_ERROR("Invalid/unknown bank number\n"); + LOG_ERROR("Invalid/unknown bank number"); return ERROR_FAIL; } @@ -1798,23 +2547,19 @@ _sam3_probe(struct flash_bank *bank, int noise) LOG_DEBUG("Here"); - r = sam3_GetInfo(pPrivate->pChip); + if (pPrivate->pChip->probed) { + r = sam3_GetInfo(pPrivate->pChip); + } else { + r = sam3_GetDetails(pPrivate); + } if (r != ERROR_OK) { return r; } - if (!(pPrivate->pChip->probed)) { - pPrivate->pChip->probed = 1; - LOG_DEBUG("Here"); - r = sam3_GetDetails(pPrivate); - if (r != ERROR_OK) { - return r; - } - } // update the flash bank size for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) { - if (bank->base == pPrivate->pChip->details.bank[0].base_address) { - bank->size = pPrivate->pChip->details.bank[0].size_bytes; + if (bank->base == pPrivate->pChip->details.bank[x].base_address) { + bank->size = pPrivate->pChip->details.bank[x].size_bytes; break; } } @@ -2046,9 +2791,7 @@ sam3_page_write_opcodes[] = { 0x10,0xf0,0x01,0x0f, // 41 0024 FBD0 beq .L4 0xfb,0xd0, - // 42 .done: - // 43 0026 FEE7 b .done - 0xfe,0xe7 + 0x00,0xBE /* bkpt #0 */ }; @@ -2057,11 +2800,28 @@ sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *b { uint32_t adr; uint32_t status; + uint32_t fmr; /* EEFC Flash Mode Register */ int r; adr = pagenum * pPrivate->page_size; adr += (adr + pPrivate->base_address); + /* Get flash mode register value */ + r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr); + if (r != ERROR_OK) + LOG_DEBUG("Error Read failed: read flash mode register"); + + /* Clear flash wait state field */ + fmr &= 0xfffff0ff; + + /* set FWS (flash wait states) field in the FMR (flash mode register) */ + fmr |= (pPrivate->flash_wait_states << 8); + + LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr))); + r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr); + if (r != ERROR_OK) + LOG_DEBUG("Error Write failed: set flash mode register"); + LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr)); r = target_write_memory(pPrivate->pChip->target, adr, @@ -2212,6 +2972,10 @@ sam3_write(struct flash_bank *bank, page_cur++; } + /* By checking that offset is correct here, we also + fix a clang warning */ + assert(offset == pPrivate->page_size); + // intermediate large pages // also - the final *terminal* // if that terminal page is a full page @@ -2258,16 +3022,13 @@ sam3_write(struct flash_bank *bank, COMMAND_HANDLER(sam3_handle_info_command) { struct sam3_chip *pChip; - void *vp; - const char *cp; - unsigned x; - int r; - pChip = get_current_sam3(CMD_CTX); if (!pChip) { return ERROR_OK; } + unsigned x; + int r; r = 0; // bank0 must exist before we can do anything @@ -2288,7 +3049,7 @@ COMMAND_HANDLER(sam3_handle_info_command) return ERROR_FAIL; } } - // above garentees the "chip details" structure is valid + // above guarantees the "chip details" structure is valid // and thus, bank private areas are valid // and we have a SAM3 chip, what a concept! @@ -2317,17 +3078,10 @@ COMMAND_HANDLER(sam3_handle_info_command) r = sam3_GetInfo(pChip); if (r != ERROR_OK) { - LOG_DEBUG("Sam3Info, Failed %d\n",r); + LOG_DEBUG("Sam3Info, Failed %d",r); return r; } - - // print results - cp = membuf_strtok(pChip->mbuf, "\n", &vp); - while (cp) { - command_print(CMD_CTX,"%s", cp); - cp = membuf_strtok(NULL, "\n", &vp); - } return ERROR_OK; } @@ -2363,7 +3117,6 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) switch (CMD_ARGC) { default: - command_print(CMD_CTX,"Too many parameters\n"); return ERROR_COMMAND_SYNTAX_ERROR; break; case 0: @@ -2386,7 +3139,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) if (0 == strcmp("show", CMD_ARGV[0])) { if (who == -1) { - showall: +showall: r = ERROR_OK; for (x = 0 ; x < pChip->details.n_gpnvms ; x++) { r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v); @@ -2418,7 +3171,7 @@ COMMAND_HANDLER(sam3_handle_gpnvm_command) (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who); } else { - command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]); + command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]); r = ERROR_COMMAND_SYNTAX_ERROR; } return r; @@ -2466,24 +3219,27 @@ COMMAND_HANDLER(sam3_handle_slowclk_command) static const struct command_registration at91sam3_exec_command_handlers[] = { { .name = "gpnvm", - .handler = &sam3_handle_gpnvm_command, + .handler = sam3_handle_gpnvm_command, .mode = COMMAND_EXEC, - .usage = "[(set|clear) []]", - .help = "Without arguments, shows the gpnvm register; " - "otherwise, sets or clear the specified bit.", + .usage = "[('clr'|'set'|'show') bitnum]", + .help = "Without arguments, shows all bits in the gpnvm " + "register. Otherwise, clears, sets, or shows one " + "General Purpose Non-Volatile Memory (gpnvm) bit.", }, { .name = "info", - .handler = &sam3_handle_info_command, + .handler = sam3_handle_info_command, .mode = COMMAND_EXEC, - .help = "print information about the current sam3 chip", + .help = "Print information about the current at91sam3 chip" + "and its flash configuration.", }, { .name = "slowclk", - .handler = &sam3_handle_slowclk_command, + .handler = sam3_handle_slowclk_command, .mode = COMMAND_EXEC, - .usage = "", - .help = "set the slowclock frequency (default 32768hz)", + .usage = "[clock_hz]", + .help = "Display or set the slowclock frequency " + "(default 32768 Hz).", }, COMMAND_REGISTRATION_DONE }; @@ -2498,15 +3254,16 @@ static const struct command_registration at91sam3_command_handlers[] = { }; struct flash_driver at91sam3_flash = { - .name = "at91sam3", - .commands = at91sam3_command_handlers, - .flash_bank_command = &sam3_flash_bank_command, - .erase = &sam3_erase, - .protect = &sam3_protect, - .write = &sam3_write, - .probe = &sam3_probe, - .auto_probe = &sam3_auto_probe, - .erase_check = &sam3_erase_check, - .protect_check = &sam3_protect_check, - .info = &sam3_info, - }; + .name = "at91sam3", + .commands = at91sam3_command_handlers, + .flash_bank_command = sam3_flash_bank_command, + .erase = sam3_erase, + .protect = sam3_protect, + .write = sam3_write, + .read = default_flash_read, + .probe = sam3_probe, + .auto_probe = sam3_auto_probe, + .erase_check = sam3_erase_check, + .protect_check = sam3_protect_check, + .info = sam3_info, +};