X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farmv4_5.h;h=6b1dd769d192c7ba87127bdd15b9d3073da86e3b;hb=cbc13187c315227c0cf8d85fb0b92d0ba4a10dab;hp=81eac476d8871d683f8b2931c28982bed4560fa6;hpb=181d401d59419ec2f5a5d89e2600d9a6dbf8f9ed;p=openocd.git

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 81eac476d8..6b1dd769d1 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -52,11 +52,12 @@ typedef enum armv4_5_state
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
@@ -69,7 +70,8 @@ enum
 	ARMV4_5_SPSR_IRQ = 33,
 	ARMV4_5_SPSR_SVC = 34,
 	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36
+	ARMV4_5_SPSR_UND = 36,
+	ARM_SPSR_MON = 39,
 };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
@@ -89,7 +91,15 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	int /* armv4_5_mode */ core_mode;
+	/**
+	 * Indicates what registers are in the ARM state core register set.
+	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+	 * more registers are shadowed, for "Secure Monitor" mode.
+	 */
+	enum armv4_5_mode core_type;
+
+	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */