X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farmv8_dpm.c;h=a5d7d11f8d0352dbbd09097a49ebc0da6cfb9b73;hb=bda2d7371874569cd5232580a3602dd56083a304;hp=ee9e1f36b85ca727feeec7f24870ac5be9e4b39d;hpb=c30f8d6a0716bb8151cd787d99dca65aa9845ed2;p=openocd.git diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index ee9e1f36b8..a5d7d11f8d 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -51,17 +51,11 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm) { int el = (dpm->dscr >> 8) & 0x3; int rw = (dpm->dscr >> 10) & 0xF; - int pos; dpm->last_el = el; - /* find the first '0' in DSCR.RW */ - for (pos = 3; pos >= 0; pos--) { - if ((rw & (1 << pos)) == 0) - break; - } - - if (el > pos) + /* In Debug state, each bit gives the current Execution state of each EL */ + if ((rw >> el) & 0b1) return ARM_STATE_AARCH64; return ARM_STATE_ARM; @@ -71,7 +65,6 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm) static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data) { - LOG_DEBUG("write DCC 0x%08" PRIx32, data); return mem_ap_write_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_DTRRX, data); } @@ -79,11 +72,10 @@ static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data) static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data) { int ret; - LOG_DEBUG("write DCC Low word 0x%08" PRIx32, (unsigned)data); - LOG_DEBUG("write DCC High word 0x%08" PRIx32, (unsigned)(data >> 32)); ret = mem_ap_write_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_DTRRX, data); - ret += mem_ap_write_u32(armv8->debug_ap, + if (ret == ERROR_OK) + ret = mem_ap_write_u32(armv8->debug_ap, armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32); return ret; } @@ -116,7 +108,6 @@ static int dpmv8_read_dcc(struct armv8_common *armv8, uint32_t *data, data); if (retval != ERROR_OK) return retval; - LOG_DEBUG("read DCC 0x%08" PRIx32, *data); if (dscr_p) *dscr_p = dscr; @@ -143,7 +134,7 @@ static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data, if (retval != ERROR_OK) return retval; if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for read dcc"); + LOG_ERROR("Timeout waiting for DTR_TX_FULL, dscr = 0x%08" PRIx32, dscr); return ERROR_FAIL; } } @@ -161,7 +152,6 @@ static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data, return retval; *data = *(uint32_t *)data | (uint64_t)higher << 32; - LOG_DEBUG("read DCC 0x%16.16" PRIx64, *data); if (dscr_p) *dscr_p = dscr; @@ -175,7 +165,7 @@ static int dpmv8_dpm_prepare(struct arm_dpm *dpm) uint32_t dscr; int retval; - /* set up invariant: INSTR_COMP is set after ever DPM operation */ + /* set up invariant: ITE is set after ever DPM operation */ long long then = timeval_ms(); for (;; ) { retval = mem_ap_read_atomic_u32(armv8->debug_ap, @@ -202,12 +192,6 @@ static int dpmv8_dpm_prepare(struct arm_dpm *dpm) armv8->debug_base + CPUV8_DBG_DTRRX, &dscr); if (retval != ERROR_OK) return retval; - - /* Clear sticky error */ - retval = mem_ap_write_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); - if (retval != ERROR_OK) - return retval; } return retval; @@ -223,11 +207,9 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm, uint32_t opcode, uint32_t *p_dscr) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; + uint32_t dscr = dpm->dscr; int retval; - LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); - if (p_dscr) dscr = *p_dscr; @@ -276,10 +258,7 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm, if (dscr & DSCR_ERR) { LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el); - /* clear the sticky error condition */ - mem_ap_write_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); - armv8_dpm_handle_exception(dpm); + armv8_dpm_handle_exception(dpm, true); retval = ERROR_FAIL; } @@ -343,96 +322,107 @@ static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm, uint32_t opcode, uint64_t data) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; int retval; - retval = dpmv8_write_dcc_64(armv8, data); - if (retval != ERROR_OK) - return retval; + if (dpm->arm->core_state != ARM_STATE_AARCH64) + return dpmv8_instr_write_data_r0(dpm, opcode, data); - retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr); - if (retval != ERROR_OK) - return retval; + /* transfer data from DCC to R0 */ + retval = dpmv8_write_dcc_64(armv8, data); + if (retval == ERROR_OK) + retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr); /* then the opcode, taking data from R0 */ - return dpmv8_exec_opcode(dpm, opcode, &dscr); + if (retval == ERROR_OK) + retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); + + return retval; } static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm) { + int retval; struct armv8_common *armv8 = dpm->arm->arch_info; + /* "Prefetch flush" after modifying execution status in CPSR */ - return dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), NULL); + retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), &dpm->dscr); + if (retval == ERROR_OK) + dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_ISB_SY), &dpm->dscr); + return retval; } static int dpmv8_instr_read_data_dcc(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; int retval; /* the opcode, writing data to DCC */ - retval = dpmv8_exec_opcode(dpm, opcode, &dscr); + retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); if (retval != ERROR_OK) return retval; - return dpmv8_read_dcc(armv8, data, &dscr); + return dpmv8_read_dcc(armv8, data, &dpm->dscr); } static int dpmv8_instr_read_data_dcc_64(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; int retval; /* the opcode, writing data to DCC */ - retval = dpmv8_exec_opcode(dpm, opcode, &dscr); + retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); if (retval != ERROR_OK) return retval; - return dpmv8_read_dcc_64(armv8, data, &dscr); + return dpmv8_read_dcc_64(armv8, data, &dpm->dscr); } static int dpmv8_instr_read_data_r0(struct arm_dpm *dpm, uint32_t opcode, uint32_t *data) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; int retval; /* the opcode, writing data to R0 */ - retval = dpmv8_exec_opcode(dpm, opcode, &dscr); + retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); if (retval != ERROR_OK) return retval; /* write R0 to DCC */ - retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dscr); + retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dpm->dscr); if (retval != ERROR_OK) return retval; - return dpmv8_read_dcc(armv8, data, &dscr); + return dpmv8_read_dcc(armv8, data, &dpm->dscr); } static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm, uint32_t opcode, uint64_t *data) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint32_t dscr = DSCR_ITE; int retval; + if (dpm->arm->core_state != ARM_STATE_AARCH64) { + uint32_t tmp; + retval = dpmv8_instr_read_data_r0(dpm, opcode, &tmp); + if (retval == ERROR_OK) + *data = tmp; + return retval; + } + /* the opcode, writing data to R0 */ - retval = dpmv8_exec_opcode(dpm, opcode, &dscr); + retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); if (retval != ERROR_OK) return retval; /* write R0 to DCC */ - retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr); + retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr); if (retval != ERROR_OK) return retval; - return dpmv8_read_dcc_64(armv8, data, &dscr); + return dpmv8_read_dcc_64(armv8, data, &dpm->dscr); } #if 0 @@ -549,62 +539,6 @@ static int dpmv8_mcr(struct target *target, int cpnum, return retval; } -static int dpmv8_mrs(struct target *target, uint32_t op0, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t *value) -{ - struct arm *arm = target_to_arm(target); - struct arm_dpm *dpm = arm->dpm; - int retval; - uint32_t op_code; - - retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - return retval; - op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\ - (CRm & 0xF) << 8 | (op2 & 0x7) << 5); - op_code >>= 5; - LOG_DEBUG("MRS p%d, %d, r0, c%d, c%d, %d", (int)op0, - (int) op1, (int) CRn, - (int) CRm, (int) op2); - /* read coprocessor register into R0; return via DCC */ - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(op_code, 0), - value); - - /* (void) */ dpm->finish(dpm); - return retval; -} - -static int dpmv8_msr(struct target *target, uint32_t op0, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t value) -{ - struct arm *arm = target_to_arm(target); - struct arm_dpm *dpm = arm->dpm; - int retval; - uint32_t op_code; - - retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - return retval; - - op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\ - (CRm & 0xF) << 8 | (op2 & 0x7) << 5); - op_code >>= 5; - LOG_DEBUG("MSR p%d, %d, r0, c%d, c%d, %d", (int)op0, - (int) op1, (int) CRn, - (int) CRm, (int) op2); - - /* read DCC into r0; then write coprocessor register from R0 */ - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(op_code, 0), - value); - - /* (void) */ dpm->finish(dpm); - return retval; -} - /*----------------------------------------------------------------------*/ /* @@ -627,12 +561,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) } else { LOG_DEBUG("setting mode 0x%"PRIx32, mode); - - /* else force to the specified mode */ - if (is_arm_mode(mode)) - cpsr = mode; - else - cpsr = mode >> 4; + cpsr = mode; } switch (cpsr & 0x1f) { @@ -644,6 +573,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) case ARM_MODE_ABT: case ARM_MODE_IRQ: case ARM_MODE_FIQ: + case ARM_MODE_SYS: target_el = 1; break; /* @@ -671,7 +601,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el); /* DCPS clobbers registers just like an exception taken */ - armv8_dpm_handle_exception(dpm); + armv8_dpm_handle_exception(dpm, false); } else { core_state = armv8_dpm_get_core_state(dpm); if (core_state != ARM_STATE_AARCH64) { @@ -721,21 +651,37 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) { struct armv8_common *armv8 = dpm->arm->arch_info; - uint64_t value_64; - int retval; + int retval = ERROR_FAIL; - retval = armv8->read_reg_u64(armv8, regnum, &value_64); + if (r->size <= 64) { + uint64_t value_64; + retval = armv8->read_reg_u64(armv8, regnum, &value_64); + + if (retval == ERROR_OK) { + r->valid = true; + r->dirty = false; + buf_set_u64(r->value, 0, r->size, value_64); + if (r->size == 64) + LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64); + else + LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64); + } + } else if (r->size <= 128) { + uint64_t lvalue = 0, hvalue = 0; + retval = armv8->read_reg_u128(armv8, regnum, &lvalue, &hvalue); + + if (retval == ERROR_OK) { + r->valid = true; + r->dirty = false; - if (retval == ERROR_OK) { - r->valid = true; - r->dirty = false; - buf_set_u64(r->value, 0, r->size, value_64); - if (r->size == 64) - LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64); - else - LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64); + buf_set_u64(r->value, 0, 64, lvalue); + buf_set_u64(r->value + 8, 0, r->size - 64, hvalue); + + LOG_DEBUG("READ: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue); + LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue); + } } - return ERROR_OK; + return retval; } /* @@ -745,20 +691,36 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) { struct armv8_common *armv8 = dpm->arm->arch_info; int retval = ERROR_FAIL; - uint64_t value_64; - value_64 = buf_get_u64(r->value, 0, r->size); + if (r->size <= 64) { + uint64_t value_64; + + value_64 = buf_get_u64(r->value, 0, r->size); + retval = armv8->write_reg_u64(armv8, regnum, value_64); - retval = armv8->write_reg_u64(armv8, regnum, value_64); - if (retval == ERROR_OK) { - r->dirty = false; - if (r->size == 64) - LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64); - else - LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64); + if (retval == ERROR_OK) { + r->dirty = false; + if (r->size == 64) + LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64); + else + LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64); + } + } else if (r->size <= 128) { + uint64_t lvalue, hvalue; + + lvalue = buf_get_u64(r->value, 0, 64); + hvalue = buf_get_u64(r->value + 8, 0, r->size - 64); + retval = armv8->write_reg_u128(armv8, regnum, lvalue, hvalue); + + if (retval == ERROR_OK) { + r->dirty = false; + + LOG_DEBUG("WRITE: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue); + LOG_DEBUG("WRITE: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue); + } } - return ERROR_OK; + return retval; } /** @@ -784,14 +746,22 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm) cache = arm->core_cache; /* read R0 first (it's used for scratch), then CPSR */ - r = cache->reg_list + 0; + r = cache->reg_list + ARMV8_R0; if (!r->valid) { - retval = dpmv8_read_reg(dpm, r, 0); + retval = dpmv8_read_reg(dpm, r, ARMV8_R0); if (retval != ERROR_OK) goto fail; } r->dirty = true; + /* read R1, too, it will be clobbered during memory access */ + r = cache->reg_list + ARMV8_R1; + if (!r->valid) { + retval = dpmv8_read_reg(dpm, r, ARMV8_R1); + if (retval != ERROR_OK) + goto fail; + } + /* read cpsr to r0 and get it back */ retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_DSPSR), &cpsr); @@ -801,13 +771,17 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm) /* update core mode and state */ armv8_set_cpsr(arm, cpsr); - for (unsigned int i = 1; i < cache->num_regs ; i++) { + for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) { struct arm_reg *arm_reg; r = armv8_reg_current(arm, i); if (r->valid) continue; + /* Skip reading FP-SIMD registers */ + if (r->number >= ARMV8_V0 && r->number <= ARMV8_FPCR) + continue; + /* * Only read registers that are available from the * current EL (or core mode). @@ -817,6 +791,10 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm) dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode)) continue; + /* Special case: ARM_MODE_SYS has no SPSR at EL1 */ + if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS) + continue; + retval = dpmv8_read_reg(dpm, r, i); if (retval != ERROR_OK) goto fail; @@ -1309,7 +1287,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr) /* ?? */ break; default: - LOG_DEBUG("Unknow core_state"); + LOG_DEBUG("Unknown core_state"); break; } dpm->wp_pc = addr; @@ -1325,7 +1303,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr) * This function must not perform any actions that trigger another exception * or a recursion will happen. */ -void armv8_dpm_handle_exception(struct arm_dpm *dpm) +void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore) { struct armv8_common *armv8 = dpm->arm->arch_info; struct reg_cache *cache = dpm->arm->core_cache; @@ -1348,6 +1326,10 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm) return; } + /* Clear sticky error */ + mem_ap_write_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); + armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr); dspsr = dlr; armv8->read_reg_u64(armv8, ARMV8_PC, &dlr); @@ -1366,6 +1348,9 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm) core_state = armv8_dpm_get_core_state(dpm); armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64); armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64); + + if (do_restore) + armv8_dpm_modeswitch(dpm, ARM_MODE_ANY); } /*----------------------------------------------------------------------*/ @@ -1443,8 +1428,6 @@ int armv8_dpm_setup(struct arm_dpm *dpm) /* coprocessor access setup */ arm->mrc = dpmv8_mrc; arm->mcr = dpmv8_mcr; - arm->mrs = dpmv8_mrs; - arm->msr = dpmv8_msr; dpm->prepare = dpmv8_dpm_prepare; dpm->finish = dpmv8_dpm_finish;