X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fmips_ejtag.h;h=694cb34479585b580298e18536ea421244fdf772;hb=f1f8d9a6c9b1fd35d79627b568faa2409f13311f;hp=6a653d4f893ff7935f5c690af42612df08d3dc3f;hpb=a8141cafdef162d52e128cd2ab51702b9800fda2;p=openocd.git

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 6a653d4f89..694cb34479 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -23,7 +23,7 @@
 #ifndef MIPS_EJTAG
 #define MIPS_EJTAG
 
-#include "jtag.h"
+#include <jtag/jtag.h>
 
 /* tap instructions */
 #define EJTAG_INST_IDCODE		0x01
@@ -40,7 +40,18 @@
 #define EJTAG_INST_TCBDATA		0x12
 #define EJTAG_INST_BYPASS		0xFF
 
-/* debug control register bits ECR */
+/* microchip PIC32MX specific instructions */
+#define MTAP_SW_MTAP			0x04
+#define MTAP_SW_ETAP			0x05
+#define MTAP_COMMAND			0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST			0xd1
+#define MCHP_DE_ASSERT_RST		0xd0
+#define MCHP_ERASE				0xfc
+#define MCHP_STATUS				0x00
+
+/* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
 #define EJTAG_CTRL_TIF			(1 << 2)
 #define EJTAG_CTRL_BRKST		(1 << 3)
@@ -87,37 +98,46 @@
 #define EJTAG_DEBUG_DBD			(1 << 31)
 
 /* implementaion register bits */
+#define EJTAG_IMP_R3K			(1 << 28)
+#define EJTAG_IMP_DINT			(1 << 24)
 #define EJTAG_IMP_NODMA			(1 << 14)
 #define EJTAG_IMP_MIPS16		(1 << 16)
+#define EJTAG_DCR_MIPS64		(1 << 0)
 
-/* breakpoint support */
+/* Debug Control Register DCR */
 #define EJTAG_DCR				0xFF300000
+#define EJTAG_DCR_ENM			(1 << 29)
+#define EJTAG_DCR_DB			(1 << 17)
+#define EJTAG_DCR_IB			(1 << 16)
+#define EJTAG_DCR_INTE			(1 << 4)
+
+/* breakpoint support */
 #define EJTAG_IBS				0xFF301000
 #define EJTAG_IBA1				0xFF301100
 #define EJTAG_DBS				0xFF302000
 #define EJTAG_DBA1				0xFF302100
-#define		EJTAG_DBCn_NOSB				(1 << 13)
-#define		EJTAG_DBCn_NOLB				(1 << 12)
-#define		EJTAG_DBCn_BLM_MASK			0xff
-#define		EJTAG_DBCn_BLM_SHIFT		4
-#define		EJTAG_DBCn_BE				(1 << 0)
+#define	EJTAG_DBCn_NOSB			(1 << 13)
+#define	EJTAG_DBCn_NOLB			(1 << 12)
+#define	EJTAG_DBCn_BLM_MASK		0xff
+#define	EJTAG_DBCn_BLM_SHIFT	4
+#define	EJTAG_DBCn_BE			(1 << 0)
 
 struct mips_ejtag
 {
 	struct jtag_tap *tap;
 	uint32_t impcode;
 	uint32_t idcode;
-	/*int use_dma;*/
 	uint32_t ejtag_ctrl;
 };
 
 int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
-		int new_instr, void *delete_me_and_submit_patch);
+		int new_instr);
 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
-int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data);
 
 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);