X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Ftarget.c;h=80e2c4cf21d06b0ce0d1b84929d162f32f46ceb0;hb=9ce207a52affec0270678808ce760450905c3f7d;hp=5b37ef03bc22b2ffabdcecae1bc6b90c1059a72c;hpb=2eb564b756bb2b7c63c1510845a42491ef82fa8d;p=openocd.git diff --git a/src/target/target.c b/src/target/target.c index 5b37ef03bc..80e2c4cf21 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -156,8 +156,6 @@ static const char *target_strerror_safe(int err) } static const Jim_Nvp nvp_target_event[] = { - { .value = TARGET_EVENT_OLD_gdb_program_config , .name = "old-gdb_program_config" }, - { .value = TARGET_EVENT_OLD_pre_resume , .name = "old-pre_resume" }, { .value = TARGET_EVENT_GDB_HALT, .name = "gdb-halt" }, { .value = TARGET_EVENT_HALTED, .name = "halted" }, @@ -168,10 +166,7 @@ static const Jim_Nvp nvp_target_event[] = { { .name = "gdb-start", .value = TARGET_EVENT_GDB_START }, { .name = "gdb-end", .value = TARGET_EVENT_GDB_END }, - /* historical name */ - - { .value = TARGET_EVENT_RESET_START, .name = "reset-start" }, - + { .value = TARGET_EVENT_RESET_START, .name = "reset-start" }, { .value = TARGET_EVENT_RESET_ASSERT_PRE, .name = "reset-assert-pre" }, { .value = TARGET_EVENT_RESET_ASSERT, .name = "reset-assert" }, { .value = TARGET_EVENT_RESET_ASSERT_POST, .name = "reset-assert-post" }, @@ -199,10 +194,6 @@ static const Jim_Nvp nvp_target_event[] = { { .value = TARGET_EVENT_GDB_FLASH_ERASE_START, .name = "gdb-flash-erase-start" }, { .value = TARGET_EVENT_GDB_FLASH_ERASE_END , .name = "gdb-flash-erase-end" }, - { .value = TARGET_EVENT_RESUME_START, .name = "resume-start" }, - { .value = TARGET_EVENT_RESUMED , .name = "resume-ok" }, - { .value = TARGET_EVENT_RESUME_END , .name = "resume-end" }, - { .name = NULL, .value = -1 } }; @@ -527,6 +518,8 @@ int target_resume(struct target *target, int current, uint32_t address, int hand return ERROR_FAIL; } + target_call_event_callbacks(target, TARGET_EVENT_RESUME_START); + /* note that resume *must* be asynchronous. The CPU can halt before * we poll. The CPU can even halt at the current PC as a result of * a software breakpoint being inserted by (a bug?) the application. @@ -535,6 +528,8 @@ int target_resume(struct target *target, int current, uint32_t address, int hand if (retval != ERROR_OK) return retval; + target_call_event_callbacks(target, TARGET_EVENT_RESUME_END); + return retval; } @@ -616,9 +611,17 @@ static int jtag_enable_callback(enum jtag_event event, void *priv) return ERROR_OK; jtag_unregister_event_callback(jtag_enable_callback, target); - return target_examine_one(target); -} + target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_START); + + int retval = target_examine_one(target); + if (retval != ERROR_OK) + return retval; + + target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_END); + + return retval; +} /* Targets that correctly implement init + examine, i.e. * no communication with target during init: @@ -637,12 +640,18 @@ int target_examine(void) target); continue; } + + target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_START); + retval = target_examine_one(target); if (retval != ERROR_OK) return retval; + + target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_END); } return retval; } + const char *target_type_name(struct target *target) { return target->type->name; @@ -796,6 +805,137 @@ done: return retval; } +/** + * Executes a target-specific native code algorithm in the target. + * It differs from target_run_algorithm in that the algorithm is asynchronous. + * Because of this it requires an compliant algorithm: + * see contrib/loaders/flash/stm32f1x.S for example. + * + * @param target used to run the algorithm + */ + +int target_run_flash_async_algorithm(struct target *target, + uint8_t *buffer, uint32_t count, int block_size, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t buffer_start, uint32_t buffer_size, + uint32_t entry_point, uint32_t exit_point, void *arch_info) +{ + int retval; + + /* Set up working area. First word is write pointer, second word is read pointer, + * rest is fifo data area. */ + uint32_t wp_addr = buffer_start; + uint32_t rp_addr = buffer_start + 4; + uint32_t fifo_start_addr = buffer_start + 8; + uint32_t fifo_end_addr = buffer_start + buffer_size; + + uint32_t wp = fifo_start_addr; + uint32_t rp = fifo_start_addr; + + /* validate block_size is 2^n */ + assert(!block_size || !(block_size & (block_size - 1))); + + retval = target_write_u32(target, wp_addr, wp); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, rp_addr, rp); + if (retval != ERROR_OK) + return retval; + + /* Start up algorithm on target and let it idle while writing the first chunk */ + retval = target_start_algorithm(target, num_mem_params, mem_params, + num_reg_params, reg_params, + entry_point, + exit_point, + arch_info); + + if (retval != ERROR_OK) { + LOG_ERROR("error starting target flash write algorithm"); + return retval; + } + + while (count > 0) { + + retval = target_read_u32(target, rp_addr, &rp); + if (retval != ERROR_OK) { + LOG_ERROR("failed to get read pointer"); + break; + } + + LOG_DEBUG("count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32, count, wp, rp); + + if (rp == 0) { + LOG_ERROR("flash write algorithm aborted by target"); + retval = ERROR_FLASH_OPERATION_FAILED; + break; + } + + if ((rp & (block_size - 1)) || rp < fifo_start_addr || rp >= fifo_end_addr) { + LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp); + break; + } + + /* Count the number of bytes available in the fifo without + * crossing the wrap around. Make sure to not fill it completely, + * because that would make wp == rp and that's the empty condition. */ + uint32_t thisrun_bytes; + if (rp > wp) + thisrun_bytes = rp - wp - block_size; + else if (rp > fifo_start_addr) + thisrun_bytes = fifo_end_addr - wp; + else + thisrun_bytes = fifo_end_addr - wp - block_size; + + if (thisrun_bytes == 0) { + /* Throttle polling a bit if transfer is (much) faster than flash + * programming. The exact delay shouldn't matter as long as it's + * less than buffer size / flash speed. This is very unlikely to + * run when using high latency connections such as USB. */ + alive_sleep(10); + continue; + } + + /* Limit to the amount of data we actually want to write */ + if (thisrun_bytes > count * block_size) + thisrun_bytes = count * block_size; + + /* Write data to fifo */ + retval = target_write_buffer(target, wp, thisrun_bytes, buffer); + if (retval != ERROR_OK) + break; + + /* Update counters and wrap write pointer */ + buffer += thisrun_bytes; + count -= thisrun_bytes / block_size; + wp += thisrun_bytes; + if (wp >= fifo_end_addr) + wp = fifo_start_addr; + + /* Store updated write pointer to target */ + retval = target_write_u32(target, wp_addr, wp); + if (retval != ERROR_OK) + break; + } + + if (retval != ERROR_OK) { + /* abort flash write algorithm on target */ + target_write_u32(target, wp_addr, 0); + } + + int retval2 = target_wait_algorithm(target, num_mem_params, mem_params, + num_reg_params, reg_params, + exit_point, + 10000, + arch_info); + + if (retval2 != ERROR_OK) { + LOG_ERROR("error waiting for target flash write algorithm"); + retval = retval2; + } + + return retval; +} int target_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) @@ -2380,7 +2520,6 @@ COMMAND_HANDLER(handle_resume_command) return ERROR_COMMAND_SYNTAX_ERROR; struct target *target = get_current_target(CMD_CTX); - target_handle_event(target, TARGET_EVENT_OLD_pre_resume); /* with no CMD_ARGV, resume from current pc, addr = 0, * with one arguments, addr = CMD_ARGV[0], @@ -4204,6 +4343,34 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return (target_fill_mem(target, a, fn, data_size, b, c) == ERROR_OK) ? JIM_OK : JIM_ERR; } +/** +* @brief Reads an array of words/halfwords/bytes from target memory starting at specified address. +* +* Usage: mdw [phys]
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