X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=NEWS;h=498797b1f4855cd5732f8789330890c487179155;hb=56c5f6361e43113846920552f5a5d2b3147ae16a;hp=a0bf43c21ff0e120ed915bc5185b1dc37d1b56b1;hpb=49036463dbebcd4c5722f89b86dc6cec777bab0f;p=openocd.git

diff --git a/NEWS b/NEWS
index a0bf43c21f..498797b1f4 100644
--- a/NEWS
+++ b/NEWS
@@ -8,12 +8,30 @@ JTAG Layer:
 
 Boundary Scan:
 Target Layer:
+	General
+		- new "reset-assert" event, for systems without SRST
 	ARM
 		- renamed "armv4_5" command prefix as "arm"
+		- recognize TrustZone "Secure Monitor" mode
+		- "arm regs" command output changed
+		- register names use "sp" not "r13"
+		- add top-level "mcr" and "mrc" commands, replacing
+		  various core-specific operations
+		- basic semihosting support
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
 		- accelerated GDB memory checksum
+		- support "arm regs" command
+		- can access all core modes and registers
+		- watchpoint support
+	Cortex-A8
+		- support "arm regs" command
+		- can access all core modes and registers
+		- supports "reset-assert" event (used on OMAP3530)
+		- watchpoint support
+	Cortex-M3
+		- Exposed DWT registers like cycle counter
 
 Flash Layer:
 	'flash bank' and 'nand device' take <bank_name> as first argument.