X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=NEWS;h=498797b1f4855cd5732f8789330890c487179155;hb=af1d7590edf04077aa8f22fba9097e0c68431f68;hp=1af13311b52663fe517dd6bd27b514b17aad07de;hpb=a65e75ea34153a8d0a0fe0b07497ad75c5726ab6;p=openocd.git

diff --git a/NEWS b/NEWS
index 1af13311b5..498797b1f4 100644
--- a/NEWS
+++ b/NEWS
@@ -17,16 +17,19 @@ Target Layer:
 		- register names use "sp" not "r13"
 		- add top-level "mcr" and "mrc" commands, replacing
 		  various core-specific operations
+		- basic semihosting support
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
 		- accelerated GDB memory checksum
 		- support "arm regs" command
 		- can access all core modes and registers
+		- watchpoint support
 	Cortex-A8
 		- support "arm regs" command
 		- can access all core modes and registers
 		- supports "reset-assert" event (used on OMAP3530)
+		- watchpoint support
 	Cortex-M3
 		- Exposed DWT registers like cycle counter