X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=doc%2Fopenocd.texi;h=2767d7874ada4e5efa56efc95100e5590ad2f2de;hb=f320b1228932e33292207d89778125c03379de5d;hp=86f5748f6076c27b705e8e845ba6c55c110620fe;hpb=d70d9634bf6ab73ec4f2ac1e77012785770b460a;p=openocd.git diff --git a/doc/openocd.texi b/doc/openocd.texi index 86f5748f60..2767d7874a 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -1502,7 +1502,7 @@ proc setc15 @{regs value@} @{ echo [format "set p15 0x%04x, 0x%08x" $regs $value] - arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \ + mcr 15 [expr ($regs>>12)&0x7] \ [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \ [expr ($regs>>8)&0x7] $value @} @@ -1975,6 +1975,42 @@ When using PPDEV to access the parallel port, use the number of the parallel por you may encounter a problem. @end deffn +@deffn Command {parport_toggling_time} [nanoseconds] +Displays how many nanoseconds the hardware needs to toggle TCK; +the parport driver uses this value to obey the +@command{jtag_khz} configuration. +When the optional @var{nanoseconds} parameter is given, +that setting is changed before displaying the current value. + +The default setting should work reasonably well on commodity PC hardware. +However, you may want to calibrate for your specific hardware. +@quotation Tip +To measure the toggling time with a logic analyzer or a digital storage +oscilloscope, follow the procedure below: +@example +> parport_toggling_time 1000 +> jtag_khz 500 +@end example +This sets the maximum JTAG clock speed of the hardware, but +the actual speed probably deviates from the requested 500 kHz. +Now, measure the time between the two closest spaced TCK transitions. +You can use @command{runtest 1000} or something similar to generate a +large set of samples. +Update the setting to match your measurement: +@example +> parport_toggling_time +@end example +Now the clock speed will be a better match for @command{jtag_khz rate} +commands given in OpenOCD scripts and event handlers. + +You can do something similar with many digital multimeters, but note +that you'll probably need to run the clock continuously for several +seconds before it decides what clock rate to show. Adjust the +toggling time up or down until the measured clock rate is a good +match for the jtag_khz rate you specified; be conservative. +@end quotation +@end deffn + @deffn {Config Command} {parport_write_on_exit} (on|off) This will configure the parallel driver to write a known cable-specific value to the parallel interface on exiting OpenOCD @@ -4584,6 +4620,32 @@ the underlying driver from applying hardware ECC. @end itemize @end deffn +@deffn Command {nand verify} num filename offset [option...] +@cindex NAND verification +@cindex NAND programming +Verify the binary data in the file has been programmed to the +specified NAND device, starting at the specified offset. +The @var{num} parameter is the value shown by @command{nand list}. + +Use a complete path name for @var{filename}, so you don't depend +on the directory used to start the OpenOCD server. + +The @var{offset} must be an exact multiple of the device's page size. +All data in the file will be read and compared to the contents of the +flash, assuming it doesn't run past the end of the device. +As with @command{nand write}, only full pages are verified, so any extra +space in the last page will be filled with 0xff bytes. + +The same @var{options} accepted by @command{nand write}, +and the file will be processed similarly to produce the buffers that +can be compared against the contents produced from @command{nand dump}. + +@b{NOTE:} This will not work when the underlying NAND controller +driver's @code{write_page} routine must update the OOB with a +hardward-computed ECC before the data is written. This limitation may +be removed in a future release. +@end deffn + @section Other NAND commands @cindex NAND other commands @@ -5051,9 +5113,11 @@ about what TAP is the current target, or about MMU configuration. Display contents of address @var{addr}, as 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}), or 8-bit bytes (@command{mdb}). +When the current target has an MMU which is present and active, +@var{addr} is interpreted as a virtual address. +Otherwise, or if the optional @var{phys} flag is specified, +@var{addr} is interpreted as a physical address. If @var{count} is specified, displays that many units. -@var{phys} is an optional flag to indicate to use -physical address and bypass MMU (If you want to manipulate the data instead of displaying it, see the @code{mem2array} primitives.) @end deffn @@ -5062,10 +5126,12 @@ see the @code{mem2array} primitives.) @deffnx Command mwh [phys] addr halfword @deffnx Command mwb [phys] addr byte Writes the specified @var{word} (32 bits), -@var{halfword} (16 bits), or @var{byte} (8-bit) pattern, +@var{halfword} (16 bits), or @var{byte} (8-bit) value, at the specified address @var{addr}. -@var{phys} is an optional flag to indicate to use -physical address and bypass MMU +When the current target has an MMU which is present and active, +@var{addr} is interpreted as a virtual address. +Otherwise, or if the optional @var{phys} flag is specified, +@var{addr} is interpreted as a physical address. @end deffn @@ -5255,11 +5321,23 @@ Several of the parameters must reflect the trace port capabilities, which are a function of silicon capabilties (exposed later using @command{etm info}) and of what hardware is connected to that port (such as an external pod, or ETB). -The @var{width} must be either 4, 8, or 16. -The @var{mode} must be @option{normal}, @option{multiplexted}, -or @option{demultiplexted}. +The @var{width} must be either 4, 8, or 16, +except with ETMv3.0 and newer modules which may also +support 1, 2, 24, 32, 48, and 64 bit widths. +(With those versions, @command{etm info} also shows whether +the selected port width and mode are supported.) + +The @var{mode} must be @option{normal}, @option{multiplexed}, +or @option{demultiplexed}. The @var{clocking} must be @option{half} or @option{full}. +@quotation Warning +With ETMv3.0 and newer, the bits set with the @var{mode} and +@var{clocking} parameters both control the mode. +This modified mode does not map to the values supported by +previous ETM modules, so this syntax is subject to change. +@end quotation + @quotation Note You can see the ETM registers using the @command{reg} command. Not all possible registers are present in every ETM. @@ -5437,16 +5515,14 @@ Reports whether the capture clock is locked or not. @end deffn -@section ARMv4 and ARMv5 Architecture -@cindex ARMv4 -@cindex ARMv5 +@section Generic ARM +@cindex ARM -These commands are specific to ARM architecture v4 and v5, -including all ARM7 or ARM9 systems and Intel XScale. +These commands should be available on all ARM processors. They are available in addition to other core-specific commands that may be available. -@deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}] +@deffn Command {arm core_state} [@option{arm}|@option{thumb}] Displays the core_state, optionally changing it to process either @option{arm} or @option{thumb} instructions. The target may later be resumed in the currently set core_state. @@ -5454,18 +5530,25 @@ The target may later be resumed in the currently set core_state. that is not currently supported in OpenOCD.) @end deffn -@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]] +@deffn Command {arm disassemble} address [count [@option{thumb}]] @cindex disassemble Disassembles @var{count} instructions starting at @var{address}. If @var{count} is not specified, a single instruction is disassembled. If @option{thumb} is specified, or the low bit of the address is set, -Thumb (16-bit) instructions are used; +Thumb2 (mixed 16/32-bit) instructions are used; else ARM (32-bit) instructions are used. (Processors may also support the Jazelle state, but those instructions are not currently understood by OpenOCD.) + +Note that all Thumb instructions are Thumb2 instructions, +so older processors (without Thumb2 support) will still +see correct disassembly of Thumb code. +Also, ThumbEE opcodes are the same as Thumb2, +with a handful of exceptions. +ThumbEE disassembly currently has no explicit support. @end deffn -@deffn Command {armv4_5 reg} +@deffn Command {arm reg} Display a table of all banked core registers, fetching the current value from every core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current register value. @@ -5796,15 +5879,6 @@ Without arguments, the current settings are displayed. @subsection ARM11 specific commands @cindex ARM11 -@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value -Write @var{value} to a coprocessor @var{pX} register -passing parameters @var{CRn}, -@var{CRm}, opcodes @var{opc1} and @var{opc2}, -and the MCR instruction. -(The difference beween this and the MCR2 instruction is -one bit in the encoding, effecively a fifth parameter.) -@end deffn - @deffn Command {arm11 memwrite burst} [value] Displays the value of the memwrite burst-enable flag, which is enabled by default. Burst writes are only used @@ -5821,15 +5895,6 @@ which is enabled by default. If @var{value} is defined, first assigns that. @end deffn -@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2 -Read a coprocessor @var{pX} register passing parameters @var{CRn}, -@var{CRm}, opcodes @var{opc1} and @var{opc2}, -and the MRC instruction. -(The difference beween this and the MRC2 instruction is -one bit in the encoding, effecively a fifth parameter.) -Displays the result. -@end deffn - @deffn Command {arm11 step_irq_enable} [value] Displays the value of the flag controlling whether IRQs are enabled during single stepping; @@ -5883,23 +5948,6 @@ Displays the number of extra tck for mem-ap memory bus access [0-255]. If @var{value} is defined, first assigns that. @end deffn -@subsection ARMv7-A specific commands -@cindex ARMv7-A - -@deffn Command {armv7a disassemble} address [count [@option{thumb}]] -@cindex disassemble -Disassembles @var{count} instructions starting at @var{address}. -If @var{count} is not specified, a single instruction is disassembled. -If @option{thumb} is specified, or the low bit of the address is set, -Thumb2 (mixed 16/32-bit) instructions are used; -else ARM (32-bit) instructions are used. -With a handful of exceptions, ThumbEE instructions are the same as Thumb2; -ThumbEE disassembly currently has no explicit support. -(Processors may also support the Jazelle state, but -those instructions are not currently understood by OpenOCD.) -@end deffn - - @subsection Cortex-M3 specific commands @cindex Cortex-M3