X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnand%2Flpc32xx.c;h=d516522f3de000b3557f6a752a1a6006c1a64909;hb=9db3e9879db3d89984eea80dc6fd9b1c3c269e58;hp=1776b309e08c9976befc15e65d3506f1d76631dd;hpb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee;p=openocd.git diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index 1776b309e0..d516522f3d 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -21,9 +21,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -44,7 +42,7 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat, * read/write data to the SLC controller. * - DMA descriptors will be put at start of working area, * - Hardware generated ECC will be stored at ECC_OFFS - * - OOB wil be read/written from/to SPARE_OFFS + * - OOB will be read/written from/to SPARE_OFFS * - Actual page data will be read from/to DATA_OFFS * There are unused holes between the used areas. */ @@ -52,10 +50,10 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat, #define SPARE_OFFS 0x140 #define DATA_OFFS 0x200 -static int sp_ooblayout[] = { +static const int sp_ooblayout[] = { 10, 11, 12, 13, 14, 15 }; -static int lp_ooblayout[] = { +static const int lp_ooblayout[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, @@ -319,7 +317,7 @@ static int lpc32xx_init(struct nand_device *nand) } /* after reset set other registers of SLC, - * so reset calling is here at the begining + * so reset calling is here at the beginning */ retval = lpc32xx_reset(nand); if (ERROR_OK != retval) @@ -334,7 +332,7 @@ static int lpc32xx_init(struct nand_device *nand) WIDTH = bus_width) */ retval = target_write_u32(target, 0x20020014, - 0x3e | (bus_width == 16) ? 1 : 0); + 0x3e | ((bus_width == 16) ? 1 : 0)); if (ERROR_OK != retval) { LOG_ERROR("could not set SLC_CFG"); return ERROR_NAND_OPERATION_FAILED; @@ -771,7 +769,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, * 2. Copy generated ECC data from Register to Spare Area * 3. X'fer next 256 bytes of data from Memory to Flash. * 4. Copy generated ECC data from Register to Spare Area. - * 5. X'fer 16 byets of Spare area from Memory to Flash. + * 5. X'fer 16 bytes of Spare area from Memory to Flash. * Read Operation Sequence for Small Block NAND * ---------------------------------------------------------- * 1. X'fer 256 bytes of data from Flash to Memory. @@ -781,13 +779,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, * 5. X'fer 16 bytes of Spare area from Flash to Memory. * Write Operation Sequence for Large Block NAND * ---------------------------------------------------------- - * 1. Steps(1-4) of Write Operations repeate for four times + * 1. Steps(1-4) of Write Operations repeated for four times * which generates 16 DMA descriptors to X'fer 2048 bytes of * data & 32 bytes of ECC data. * 2. X'fer 64 bytes of Spare area from Memory to Flash. * Read Operation Sequence for Large Block NAND * ---------------------------------------------------------- - * 1. Steps(1-4) of Read Operations repeate for four times + * 1. Steps(1-4) of Read Operations repeated for four times * which generates 16 DMA descriptors to X'fer 2048 bytes of * data & 32 bytes of ECC data. * 2. X'fer 64 bytes of Spare area from Flash to Memory. @@ -844,7 +842,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, * 2. Copy generated ECC data from Register to Spare Area * 3. X'fer next 256 bytes of data from Memory to Flash. * 4. Copy generated ECC data from Register to Spare Area. - * 5. X'fer 16 byets of Spare area from Memory to Flash. + * 5. X'fer 16 bytes of Spare area from Memory to Flash. * Read Operation Sequence for Small Block NAND * ---------------------------------------------------------- * 1. X'fer 256 bytes of data from Flash to Memory. @@ -854,13 +852,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size, * 5. X'fer 16 bytes of Spare area from Flash to Memory. * Write Operation Sequence for Large Block NAND * ---------------------------------------------------------- - * 1. Steps(1-4) of Write Operations repeate for four times + * 1. Steps(1-4) of Write Operations repeated for four times * which generates 16 DMA descriptors to X'fer 2048 bytes of * data & 32 bytes of ECC data. * 2. X'fer 64 bytes of Spare area from Memory to Flash. * Read Operation Sequence for Large Block NAND * ---------------------------------------------------------- - * 1. Steps(1-4) of Read Operations repeate for four times + * 1. Steps(1-4) of Read Operations repeated for four times * which generates 16 DMA descriptors to X'fer 2048 bytes of * data & 32 bytes of ECC data. * 2. X'fer 64 bytes of Spare area from Flash to Memory. @@ -1040,13 +1038,13 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, int retval; uint32_t target_mem_base; - LOG_DEBUG("SLC write page %x data=%d, oob=%d, " - "data_size=%d, oob_size=%d", + LOG_DEBUG("SLC write page %" PRIx32 " data=%d, oob=%d, " + "data_size=%" PRIu32 ", oob_size=%" PRIu32, page, data != 0, oob != 0, data_size, oob_size); target_mem_base = pworking_area->address; /* - * Skip writting page which has all 0xFF data as this will + * Skip writing page which has all 0xFF data as this will * generate 0x0 value. */ if (data && !oob) { @@ -1104,7 +1102,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, return retval; } - /* Write first decriptor to DMA controller */ + /* Write first descriptor to DMA controller */ retval = target_write_memory(target, 0x31000100, 4, sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist); @@ -1148,7 +1146,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, /* Copy to oob, at correct offsets */ static uint8_t ecc[24]; slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count); - int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout; + const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout; int i; for (i = 0; i < ecc_count * 3; i++) foob[layout[i]] = ecc[i]; @@ -1161,7 +1159,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand, return retval; } - /* Write OOB decriptor to DMA controller */ + /* Write OOB descriptor to DMA controller */ retval = target_write_memory(target, 0x31000100, 4, sizeof(dmac_ll_t) / 4, (uint8_t *)(&dmalist[nll-1])); @@ -1451,7 +1449,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, int retval; uint32_t target_mem_base; - LOG_DEBUG("SLC read page %x data=%d, oob=%d", + LOG_DEBUG("SLC read page %" PRIx32 " data=%" PRIu32 ", oob=%" PRIu32, page, data_size, oob_size); target_mem_base = pworking_area->address; @@ -1489,7 +1487,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, return retval; } - /* Write first decriptor to DMA controller */ + /* Write first descriptor to DMA controller */ retval = target_write_memory(target, 0x31000100, 4, sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist); if (ERROR_OK != retval) { @@ -1549,7 +1547,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count); /* Copy ECC from flash using correct layout */ static uint8_t fecc[24];/* max size */ - int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout; + const int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout; int i; for (i = 0; i < ecc_count * 3; i++) fecc[i] = foob[layout[i]]; @@ -1558,7 +1556,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3], &ecc[i * 3]); if (retval > 0) - LOG_WARNING("error detected and corrected: %d/%d", + LOG_WARNING("error detected and corrected: %" PRIu32 "/%d", page, i); if (retval < 0) break; @@ -1566,7 +1564,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand, if (i == ecc_count) retval = ERROR_OK; else { - LOG_ERROR("uncorrectable error detected: %d/%d", page, i); + LOG_ERROR("uncorrectable error detected: %" PRIu32 "/%d", page, i); retval = ERROR_NAND_OPERATION_FAILED; } return retval; @@ -1762,7 +1760,7 @@ COMMAND_HANDLER(handle_lpc32xx_select_command) COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct nand_device *nand = get_nand_device_by_num(num); if (!nand) { - command_print(CMD_CTX, "nand device '#%s' is out of bounds", + command_print(CMD, "nand device '#%s' is out of bounds", CMD_ARGV[0]); return ERROR_OK; } @@ -1780,7 +1778,7 @@ COMMAND_HANDLER(handle_lpc32xx_select_command) return ERROR_COMMAND_SYNTAX_ERROR; } - command_print(CMD_CTX, "%s controller selected", + command_print(CMD, "%s controller selected", selected[lpc32xx_info->selected_controller]); return ERROR_OK;