X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91sam3.c;h=c46829eff6933ed297abccadefc3ac63bf9ce282;hb=811f7d3f7eb0a2f40406949e21d7f2ab577d2d46;hp=221832ce600823c522e1548549145609d744a85d;hpb=2986320cde399b0b0ee006a4fecbdec83bebc248;p=openocd.git

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 221832ce60..c46829eff6 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -62,7 +62,6 @@
 
 
 #include "imp.h"
-#include "at91sam3.h"
 #include <helper/time_support.h>
 
 #define REG_NAME_WIDTH  (12)
@@ -74,6 +73,9 @@
 // at91sam3s series (has always one flash bank)
 #define FLASH_BANK_BASE_S   0x00400000
 
+// at91sam3n series (has always one flash bank)
+#define FLASH_BANK_BASE_N   0x00400000
+
 #define 	AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
 #define 	AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
 #define 	AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
@@ -99,6 +101,8 @@
 #define  offset_EFC_FRR   12
 
 
+extern struct flash_driver at91sam3_flash;
+
 static float
 _tomhz(uint32_t freq_hz)
 {
@@ -831,6 +835,440 @@ static const struct sam3_chip_details all_sam3_details[] = {
 		  },
 		},
 	},
+
+	// Start at91sam3n* series
+	{
+		.chipid_cidr    = 0x29540960,
+		.name           = "at91sam3n4c",
+		.total_flash_size     = 256 * 1024,
+		.total_sram_size      = 24 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 256 * 1024,
+			.nsectors   = 16,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29440960,
+		.name           = "at91sam3n4b",
+		.total_flash_size     = 256 * 1024,
+		.total_sram_size      = 24 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 256 * 1024,
+			.nsectors   = 16,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29340960,
+		.name           = "at91sam3n4a",
+		.total_flash_size     = 256 * 1024,
+		.total_sram_size      = 24 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 256 * 1024,
+			.nsectors   = 16,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29590760,
+		.name           = "at91sam3n2c",
+		.total_flash_size     = 128 * 1024,
+		.total_sram_size      = 16 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 128 * 1024,
+			.nsectors   = 8,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29490760,
+		.name           = "at91sam3n2b",
+		.total_flash_size     = 128 * 1024,
+		.total_sram_size      = 16 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 128 * 1024,
+			.nsectors   = 8,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29390760,
+		.name           = "at91sam3n2a",
+		.total_flash_size     = 128 * 1024,
+		.total_sram_size      = 16 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 128 * 1024,
+			.nsectors   = 8,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29580560,
+		.name           = "at91sam3n1c",
+		.total_flash_size     = 64 * 1024,
+		.total_sram_size      = 8 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 64 * 1024,
+			.nsectors   = 4,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29480560,
+		.name           = "at91sam3n1b",
+		.total_flash_size     = 64 * 1024,
+		.total_sram_size      = 8 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 64 * 1024,
+			.nsectors   = 4,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
+	{
+		.chipid_cidr    = 0x29380560,
+		.name           = "at91sam3n1a",
+		.total_flash_size     = 64 * 1024,
+		.total_sram_size      = 8 * 1024,
+		.n_gpnvms       = 3,
+		.n_banks        = 1,
+
+		// System boots at address 0x0
+		// gpnvm[1] = selects boot code
+		//     if gpnvm[1] == 0
+		//         boot is via "SAMBA" (rom)
+		//     else
+		//         boot is via FLASH
+		//         Selection is via gpnvm[2]
+		//     endif
+		//
+		// NOTE: banks 0 & 1 switch places
+		//     if gpnvm[2] == 0
+		//         Bank0 is the boot rom
+		//      else
+		//         Bank1 is the boot rom
+		//      endif
+//		.bank[0] = {
+		{
+		  {
+			.probed = 0,
+			.pChip  = NULL,
+			.pBank  = NULL,
+			.bank_number = 0,
+			.base_address = FLASH_BANK_BASE_N,
+			.controller_address = 0x400e0A00,
+			.present = 1,
+			.size_bytes = 64 * 1024,
+			.nsectors   = 4,
+			.sector_size = 16384,
+			.page_size   = 256,
+		  },
+
+//		.bank[1] = {
+		  {
+		  	.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+		  },
+		},
+	},
+
 	// terminate
 	{
 		.chipid_cidr	= 0,
@@ -1458,16 +1896,16 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 	uint32_t rcen;
 
 	v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
-	LOG_USER_N("(main xtal enabled: %s)\n",
+	LOG_USER("(main xtal enabled: %s)",
 				  _yes_or_no(v));
 	v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
-	LOG_USER_N("(main osc bypass: %s)\n",
+	LOG_USER("(main osc bypass: %s)",
 				  _yes_or_no(v));
-	rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
-	LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
+	rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
+	LOG_USER("(onchip RC-OSC enabled: %s)",
 				  _yes_or_no(rcen));
 	v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
-	LOG_USER_N("(onchip RC-OSC freq: %s)\n",
+	LOG_USER("(onchip RC-OSC freq: %s)",
 				  _rc_freq[v]);
 
 	pChip->cfg.rc_freq = 0;
@@ -1475,6 +1913,7 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 		switch (v) {
 		default:
 			pChip->cfg.rc_freq = 0;
+			break;
 		case 0:
 			pChip->cfg.rc_freq = 4 * 1000 * 1000;
 			break;
@@ -1488,14 +1927,14 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 	}
 
 	v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
-	LOG_USER_N("(startup clks, time= %f uSecs)\n",
+	LOG_USER("(startup clks, time= %f uSecs)",
 				  ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
 	v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
-	LOG_USER_N("(mainosc source: %s)\n",
+	LOG_USER("(mainosc source: %s)",
 				  v ? "external xtal" : "internal RC");
 
 	v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
-	LOG_USER_N("(clock failure enabled: %s)\n",
+	LOG_USER("(clock failure enabled: %s)",
 				 _yes_or_no(v));
 }
 
@@ -1512,16 +1951,16 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
 	LOG_USER_N("\n");
 
 	v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
-	LOG_USER_N("%s\n", eproc_names[v]);
+	LOG_USER("%s", eproc_names[v]);
 
 	v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
-	LOG_USER_N("%s\n", nvpsize[v]);
+	LOG_USER("%s", nvpsize[v]);
 
 	v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
-	LOG_USER_N("%s\n", nvpsize2[v]);
+	LOG_USER("%s", nvpsize2[v]);
 
 	v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
-	LOG_USER_N("%s\n", sramsize[ v ]);
+	LOG_USER("%s", sramsize[ v ]);
 
 	v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
 	cp = _unknown;
@@ -1532,13 +1971,13 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
 		}
 	}
 
-	LOG_USER_N("%s\n", cp);
+	LOG_USER("%s", cp);
 
 	v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
-	LOG_USER_N("%s\n", nvptype[ v ]);
+	LOG_USER("%s", nvptype[ v ]);
 
 	v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
-	LOG_USER_N("(exists: %s)\n", _yes_or_no(v));
+	LOG_USER("(exists: %s)", _yes_or_no(v));
 }
 
 static void
@@ -1548,14 +1987,14 @@ sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
 
 
 	v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
-	LOG_USER_N("(main ready: %s)\n", _yes_or_no(v));
+	LOG_USER("(main ready: %s)", _yes_or_no(v));
 
 	v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
 
 	v = (v * pChip->cfg.slow_freq) / 16;
 	pChip->cfg.mainosc_freq = v;
 
-	LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
+	LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
 				 _tomhz(v),
 				 pChip->cfg.slow_freq / 1000,
 				 pChip->cfg.slow_freq % 1000);
@@ -1573,12 +2012,12 @@ sam3_explain_ckgr_plla(struct sam3_chip *pChip)
 	LOG_USER_N("\n");
 	pChip->cfg.plla_freq = 0;
 	if (mula == 0) {
-		LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
+		LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
 	} else if (diva == 0) {
-		LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
+		LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
 	} else if (diva == 1) {
 		pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
-		LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
+		LOG_USER("\tPLLA Freq: %3.03f MHz",
 					 _tomhz(pChip->cfg.plla_freq));
 	}
 }
@@ -1619,7 +2058,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
 		break;
 	}
 
-	LOG_USER_N("%s (%3.03f Mhz)\n",
+	LOG_USER("%s (%3.03f Mhz)",
 				  cp,
 				  _tomhz(fin));
 	pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
@@ -1627,6 +2066,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
 	case 0:
 		pdiv = 1;
 		cp = "selected clock";
+		break;
 	case 1:
 		pdiv = 2;
 		cp = "clock/2";
@@ -1659,14 +2099,14 @@ sam3_explain_mckr(struct sam3_chip *pChip)
 		assert(0);
 		break;
 	}
-	LOG_USER_N("(%s)\n", cp);
+	LOG_USER("(%s)", cp);
 	fin = fin / pdiv;
 	// sam3 has a *SINGLE* clock -
 	// other at91 series parts have divisors for these.
 	pChip->cfg.cpu_freq = fin;
 	pChip->cfg.mclk_freq = fin;
 	pChip->cfg.fclk_freq = fin;
-	LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
+	LOG_USER("\t\tResult CPU Freq: %3.03f",
 				  _tomhz(fin));
 }
 
@@ -1702,7 +2142,7 @@ sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
 	// By using prototypes - we can detect what would
 	// be casting errors.
 
-	return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
+	return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
 }
 
 
@@ -1756,7 +2196,7 @@ sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
 		// calculate where this one go..
 		// it is "possibly" this register.
 
-		pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
+		pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
 
 		// well? Is it this register
 		if (pPossible == goes_here) {
@@ -1786,7 +2226,7 @@ sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
 
 	r = target_read_u32(pChip->target, pReg->address, goes_here);
 	if (r != ERROR_OK) {
-		LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
+		LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
 				  pReg->name, (unsigned)(pReg->address), r);
 	}
 	return r;
@@ -1805,7 +2245,7 @@ sam3_ReadAllRegs(struct sam3_chip *pChip)
 		r = sam3_ReadThisReg(pChip,
 								  sam3_get_reg_ptr(&(pChip->cfg), pReg));
 		if (r != ERROR_OK) {
-			LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
+			LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
 					  pReg->name, ((unsigned)(pReg->address)), r);
 			return r;
 		}
@@ -1828,7 +2268,7 @@ sam3_GetInfo(struct sam3_chip *pChip)
 		// display all regs
 		LOG_DEBUG("Start: %s", pReg->name);
 		regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
-		LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
+		LOG_USER("%*s: [0x%08x] -> 0x%08x",
 					 REG_NAME_WIDTH,
 					 pReg->name,
 					 pReg->address,
@@ -1839,14 +2279,14 @@ sam3_GetInfo(struct sam3_chip *pChip)
 		LOG_DEBUG("End: %s", pReg->name);
 		pReg++;
 	}
-	LOG_USER_N("   rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
-	LOG_USER_N("  mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
-	LOG_USER_N("     plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
-	LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
-	LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
+	LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
+	LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
+	LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
+	LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
+	LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
 
 
-	LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+	LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
 				  pChip->cfg.unique_id[0],
 				  pChip->cfg.unique_id[1],
 				  pChip->cfg.unique_id[2],
@@ -1868,7 +2308,7 @@ sam3_erase_check(struct flash_bank *bank)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	if (0 == bank->num_sectors) {
-		LOG_ERROR("Target: not supported/not probed\n");
+		LOG_ERROR("Target: not supported/not probed");
 		return ERROR_FAIL;
 	}
 
@@ -1971,6 +2411,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
 		bank->bank_number = 1;
 		pChip->details.bank[1].pChip = pChip;
 		pChip->details.bank[1].pBank = bank;
+		break;
 
 	// at91sam3s series
 	case FLASH_BANK_BASE_S:
@@ -1996,7 +2437,8 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
 	LOG_DEBUG("Begin");
 	pDetails = all_sam3_details;
 	while (pDetails->name) {
-		if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
+		// Compare cidr without version bits
+		if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0)) {
 			break;
 		} else {
 			pDetails++;
@@ -2006,7 +2448,7 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
 		LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
 				  (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
 		// Help the victim, print details about the chip
-		LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
+		LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
 						pPrivate->pChip->cfg.CHIPID_CIDR);
 		sam3_explain_chipid_cidr(pPrivate->pChip);
 		return ERROR_FAIL;
@@ -2065,7 +2507,7 @@ _sam3_probe(struct flash_bank *bank, int noise)
 
 	pPrivate = get_sam3_bank_private(bank);
 	if (!pPrivate) {
-		LOG_ERROR("Invalid/unknown bank number\n");
+		LOG_ERROR("Invalid/unknown bank number");
 		return ERROR_FAIL;
 	}
 
@@ -2087,8 +2529,8 @@ _sam3_probe(struct flash_bank *bank, int noise)
 
 	// update the flash bank size
 	for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
-		if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
-			bank->size =  pPrivate->pChip->details.bank[0].size_bytes;
+		if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
+			bank->size =  pPrivate->pChip->details.bank[x].size_bytes;
 			break;
 		}
 	}
@@ -2587,7 +3029,7 @@ COMMAND_HANDLER(sam3_handle_info_command)
 
 	r = sam3_GetInfo(pChip);
 	if (r != ERROR_OK) {
-		LOG_DEBUG("Sam3Info, Failed %d\n",r);
+		LOG_DEBUG("Sam3Info, Failed %d",r);
 		return r;
 	}
 
@@ -2681,7 +3123,7 @@ showall:
 			   (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
 		r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
 	} else {
-		command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
+		command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
 		r = ERROR_COMMAND_SYNTAX_ERROR;
 	}
 	return r;